公开(公告)号：US07984248B2

公开(公告)日：2011-07-19

申请号：US11027623

申请日：2004-12-29

Applicant: Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

Inventor： Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

IPC: G06F12/00

CPC classification number: G06F9/528 ,  G06F9/3834 ,  G06F9/544

Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are track by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

Abstract translation: 本文描述的装置和方法用于通过事务执行来处理利用无锁同步的多个处理器之间的共享存储器访问。 在软件中划分的事务被推测执行。 在执行期间，无效远程访问/请求到从共享存储器加载并被写入到共享存储器的地址由事务缓冲器跟踪。 如果遇到无效访问，则重新执行该事务。 在重新执行事务的预定次数之后，可以非推测地用锁/信号量重新执行事务。

公开(公告)号：US07669009B2

公开(公告)日：2010-02-23

申请号：US10950279

申请日：2004-09-23

Applicant: Sailesh Kottapalli ,  John H. Crawford

Inventor： Sailesh Kottapalli ,  John H. Crawford

IPC: G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0811 ,  G06F12/123

Abstract: A method and apparatus for selecting and updating a replacement candidate in a cache is disclosed. In one embodiment, a cache miss may initiate the eviction of a present replacement candidate in a last-level cache. The cache miss may also initiate the selection of a future replacement candidate. Upon the selection of the future replacement candidate, the corresponding cache line may be invalidated in lower-level caches but remain resident in the last-level cache. The future replacement candidate may be updated by subsequent hits to the replacement candidate in the last-level cache prior to a subsequent cache miss.

Abstract translation: 公开了一种用于选择和更新高速缓存中的替换候选的方法和装置。 在一个实施例中，高速缓存未命中可以在最后一级高速缓存中启动对当前替换候选者的驱逐。 高速缓存未命中还可以启动未来替换候选者的选择。 在选择将来的替换候选者之后，相应的高速缓存行可能在较低级别的高速缓存中被无效，但仍然驻留在最后一级高速缓存中。 在随后的高速缓存未命中之前，可以通过对最后一级高速缓存中的替换候选者的后续命中来更新未来替换候选。

公开(公告)号：US07496732B2

公开(公告)日：2009-02-24

申请号：US10739686

申请日：2003-12-17

Applicant: Sailesh Kottapalli ,  Richard W. Goe ,  Youngsoo Choi

Inventor： Sailesh Kottapalli ,  Richard W. Goe ,  Youngsoo Choi

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3861

Abstract: A method and apparatus for using result-speculative data under run-ahead speculative execution is disclosed. In one embodiment, the uncommitted target data from instructions being run-ahead executed may be saved into an advance data table. This advance data table may be indexed by the lines in the instruction buffer containing the instructions for run-ahead execution. When the instructions are re-executed subsequent to the run-ahead execution, valid target data may be retrieved from the advance data table and supplied as part of a zero-clock bypass to support parallel re-execution. This may achieve parallel execution of dependent instructions. In other embodiments, the advance data table may be content-addressable-memory searchable on target registers and supply target data to general speculative execution.

Abstract translation: 公开了一种在预先推测执行下使用结果推测数据的方法和装置。 在一个实施例中，来自正在执行的预定指令的未提交的目标数据可以被保存到提前数据表中。 该提前数据表可以由包含用于预先执行的指令的指令缓冲器中的行进行索引。 当在超前执行之后重新执行指令时，可以从提前数据表检索有效的目标数据，并作为零时钟旁路的一部分提供以支持并行重新执行。 这可以实现依赖指令的并行执行。 在其他实施例中，提前数据表可以是内容寻址存储器，可在目标寄存器上搜索，并将目标数据提供给一般推测执行。

公开(公告)号：US20050210905A1

公开(公告)日：2005-09-29

申请号：US10808882

申请日：2004-03-24

Applicant: James Burns ,  Sailesh Kottapalli

Inventor： James Burns ,  Sailesh Kottapalli

IPC: F25B19/02 ,  F25D23/12 ,  G06F1/20 ,  G06F1/32 ,  H01L23/34

CPC classification number: G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  H01L23/34 ,  H01L2924/0002 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172 ,  H01L2924/00

Abstract: A system may include a first portion and a processor. The first portion may include a first thermal sensor to provide first thermal data. The processor may include a core, a core thermal sensor to provide core thermal data, and an electrical power sensor to provide electrical data. The processor may also include a power management unit to selectively throttle the core based on the first thermal data, the core thermal data, and the electrical data.

Abstract translation: 系统可以包括第一部分和处理器。 第一部分可以包括第一热传感器以提供第一热数据。 处理器可以包括芯，提供核心热数据的核心热传感器，以及提供电数据的电功率传感器。 处理器还可以包括功率管理单元，用于基于第一热数据，核心热数据和电数据来选择性地调节核心。

公开(公告)号：US06898694B2

公开(公告)日：2005-05-24

申请号：US09896346

申请日：2001-06-28

Applicant: Sailesh Kottapalli ,  James S. Burns ,  Kenneth D. Shoemaker

Inventor： Sailesh Kottapalli ,  James S. Burns ,  Kenneth D. Shoemaker

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/3806 ,  G06F9/3802 ,  G06F9/3851

Abstract: The present invention provides a mechanism for supporting high bandwidth instruction fetching in a multi-threaded processor. A multi-threaded processor includes an instruction cache (I-cache) and a temporary instruction cache (TIC). In response to an instruction pointer (IP) of a first thread hitting in the I-cache, a first block of instructions for the thread is provided to an instruction buffer and a second block of instructions for the thread are provided to the TIC. On a subsequent clock interval, the second block of instructions is provided to the instruction buffer, and first and second blocks of instructions from a second thread are loaded into a second instruction buffer and the TIC, respectively.

Abstract translation: 本发明提供一种用于在多线程处理器中支持高带宽指令提取的机制。 多线程处理器包括指令高速缓存（I-cache）和临时指令高速缓存（TIC）。 响应于在I缓存中击中的第一线程的指令指针（IP），将线程的第一指令块提供给指令缓冲器，并且向TIC提供用于线程的第二指令块。 在随后的时钟间隔中，第二指令块被提供给指令缓冲器，并且来自第二线程的第一和第二指令块分别被加载到第二指令缓冲器和TIC中。

公开(公告)号：US06721873B2

公开(公告)日：2004-04-13

申请号：US09753060

申请日：2000-12-29

Applicant: Sailesh Kottapalli ,  Udo Walterscheidt ,  Andrew Sun ,  Thomas Yeh ,  Kinkee Sit

Inventor： Sailesh Kottapalli ,  Udo Walterscheidt ,  Andrew Sun ,  Thomas Yeh ,  Kinkee Sit

IPC: G06F938

CPC classification number: G06F9/3885 ,  G06F9/3853

Abstract: A method and apparatus for improving dispersal performance of instruction threads is described. In one embodiment, the dispersal logic determines whether the instructions supplied to it include any NOP instructions. When a NOP instruction is detected, the dispersal logic places the NOP into a no-op port for execution. All other instructions are distributed to the proper execution pipes in a normal manner. Because the NOP instructions do not use the execution resources of other instructions, all instruction threads can be executed in one cycle.

公开(公告)号：US09201748B2

公开(公告)日：2015-12-01

申请号：US13996717

申请日：2012-03-30

Applicant: Brian S. Morris ,  Sailesh Kottapalli

Inventor： Brian S. Morris ,  Sailesh Kottapalli

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/16

CPC classification number: G06F11/2094 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/20 ,  G06F2201/815

Abstract: Systems and techniques for virtual device sharing. A failure of one of a plurality of memory devices corresponding to a first rank in a memory system is detected. The memory system has a plurality of ranks, each rank having a plurality of memory devices used to store a cache line. A portion of the cache line corresponding to the failed memory device is stored in a memory device in a second rank in the memory system and the remaining portion of the cache line in the first rank of the memory system.

Abstract translation: 用于虚拟设备共享的系统和技术。 检测到与存储器系统中的第一等级对应的多个存储器件中的一个的故障。 存储器系统具有多个等级，每个等级具有用于存储高速缓存行的多个存储器件。 对应于故障存储器件的高速缓存线的一部分被存储在存储器系统中的第二等级的存储器件中，并且存储器系统的第一级中的高速缓存行的剩余部分被存储。

公开(公告)号：US08458412B2

公开(公告)日：2013-06-04

申请号：US13168171

申请日：2011-06-24

Applicant: Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

Inventor： Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

IPC: G06F12/00

CPC classification number: G06F9/528 ,  G06F9/3834 ,  G06F9/544

Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

Abstract translation: 本文描述的装置和方法用于通过事务执行来处理利用无锁同步的多个处理器之间的共享存储器访问。 在软件中划分的事务被推测执行。 在执行期间，无效远程访问/请求到从共享存储器加载并被写入到共享存储器的地址由事务缓冲器跟踪。 如果遇到无效访问，则重新执行该事务。 在重新执行事务的预定次数之后，可以非推测地用锁/信号量重新执行事务。

公开(公告)号：US20130007376A1

公开(公告)日：2013-01-03

申请号：US13175787

申请日：2011-07-01

Applicant: SAILESH KOTTAPALLI ,  VEDARAMAN GEETHA ,  HENK G. NEEFS ,  YOUNGSOO CHOI

Inventor： SAILESH KOTTAPALLI ,  VEDARAMAN GEETHA ,  HENK G. NEEFS ,  YOUNGSOO CHOI

IPC: G06F12/08

CPC classification number: G06F12/0833

Abstract: Methods and apparatus relating to Opportunistic Snoop Broadcast (OSB) in directory enabled home snoopy systems are described. In one embodiment, a plurality of snoops are broadcast to a plurality of caching agents in response to a request for data and based on a comparison of a bandwidth consumption of the link and a threshold value. Other embodiments are also disclosed.

Abstract translation: 描述了与启用目录的家庭侦探系统相关的机会侦听广播（OSB）的方法和设备。 在一个实施例中，响应于对数据的请求并且基于链路的带宽消耗与阈值的比较，将多个窥探广播到多个高速缓存代理。 还公开了其他实施例。

公开(公告)号：US08176266B2

公开(公告)日：2012-05-08

申请号：US12943314

申请日：2010-11-10

Applicant: Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

Inventor： Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

IPC: G06F12/00

CPC classification number: G06F9/528 ,  G06F9/3834 ,  G06F9/544

Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

Abstract translation: 本文描述的装置和方法用于通过事务执行来处理利用无锁同步的多个处理器之间的共享存储器访问。 在软件中划分的事务被推测执行。 在执行期间，无效远程访问/请求到从共享存储器加载并被写入到共享存储器的地址由事务缓冲器跟踪。 如果遇到无效访问，则重新执行该事务。 在重新执行事务的预定次数之后，可以非推测地用锁/信号量重新执行事务。