公开(公告)号：US20050270870A1

公开(公告)日：2005-12-08

申请号：US11143391

申请日：2005-06-01

Applicant: Sangho Shin ,  Sangho Lee ,  Kee Park

Inventor： Sangho Shin ,  Sangho Lee ,  Kee Park

IPC: G11C7/00 ,  H04Q11/04

CPC classification number: H04Q11/0421 ,  H04Q2213/13103 ,  H04Q2213/13216 ,  H04Q2213/13292 ,  H04Q2213/13393

Abstract: In accordance with the invention, time slot interchange switches (“TSIS”) with a cache memory are described. A time slot interchange switch according to the present invention can include a data memory that receives and stores at least one stream of channel data; a cache memory that receives the at least one stream of channel data; and a microprocessor interface coupled to read data from the cache memory. Accordingly, a method of reading data from a time slot interchange switch to a microprocessor can include writing channel data to a cache memory in addition to a data memory; and providing data from the cache memory in response to requests from a microprocessor interface.

Abstract translation: 根据本发明，描述了具有高速缓冲存储器的时隙交换开关（“TSIS”）。 根据本发明的时隙交换交换机可以包括接收并存储至少一个信道数据流的数据存储器; 高速缓存存储器，其接收所述至少一个信道数据流; 以及耦合到从高速缓冲存储器读取数据的微处理器接口。 因此，从时隙交换开关向微处理器读取数据的方法可以包括除了数据存储器之外还将信道数据写入高速缓存存储器; 以及响应于来自微处理器接口的请求，从高速缓冲存储器提供数据。

公开(公告)号：US5588054A

公开(公告)日：1996-12-24

申请号：US425530

申请日：1995-04-20

Applicant: Seongkee Shin ,  Sangho Lee

Inventor： Seongkee Shin ,  Sangho Lee

IPC: H04M11/00 ,  G06F1/32 ,  G06F3/00 ,  H04L12/10 ,  H04M11/06

CPC classification number: G06F1/3209 ,  H04L12/10 ,  H04M11/06

Abstract: A power conservation system for a modem in a computer system having a primary power supply and an auxiliary power supply, including a ring detect circuit coupled to a telephone ring signal line for generating a ring detect signal in response to detection of a ring signal on the telephone ring signal line, a power management system having an input coupled to the ring detect circuit and an output coupled to the primary power supply, the power management system being responsive to the ring detect signal for switching the primary power supply from a first level corresponding to a power conservation mode of operation of the computer system to a second level corresponding to a normal mode of operation, wherein the auxiliary power supply is coupled to the ring detect circuit for supplying power thereto when the computer system is in the power conservation mode of operation, whereby the ring detect circuit is maintained in an active state even during the power conservation mode of operation of the computer system.

Abstract translation: 一种用于具有主电源和辅助电源的计算机系统中的调制解调器的功率节省系统，包括耦合到电话环信号线的环形检测电路，用于响应于在所述电路环上的振铃信号的检测而产生振铃检测信号 电话铃声信号线，具有耦合到环形检测电路的输入和耦合到主电源的输出的电力管理系统，所述电力管理系统响应于所述环形检测信号，用于从所述第一电平相应地切换所述主电源 到计算机系统的功率节省模式为对应于正常操作模式的第二电平，其中当计算机系统处于功率保存模式时，辅助电源耦合到环路检测电路以供电， 从而即使在功率保持操作模式下，环路检测电路也保持在活动状态 计算机系统。

公开(公告)号：US20230138959A1

公开(公告)日：2023-05-04

申请号：US17976514

申请日：2022-10-28

Applicant: Pedamalli SAIKRISHNA ,  Ankur Goyal ,  Ashok Kumar Reddy Chavva ,  Ashwini Kumar ,  Suhwook Kim ,  Sangho Lee

Inventor： Pedamalli SAIKRISHNA ,  Ankur Goyal ,  Ashok Kumar Reddy Chavva ,  Ashwini Kumar ,  Suhwook Kim ,  Sangho Lee

IPC: H03F3/26 ,  G06K9/62 ,  G06N3/04

Abstract: Embodiments herein disclose a method for controlling a non-linear effect of a power amplifier by an apparatus. The method includes acquiring an input data of the power amplifier of the apparatus and an output data of the power amplifier. Further, the method includes determining an inverse function using a neural network. The inverse function maps normalized output data of the PA to the input data of the PA, where the neural network comprises at least one sub-network for at least one memory tap from a plurality of memory taps in the neural network. Further, the method includes modifying the input data based on the determined inverse function value by dynamically changing a usage of the at least one memory tap from the plurality of memory taps. Further, the method includes compensating the non-linear effect in the output data of the power amplifier.

公开(公告)号：US11629464B2

公开(公告)日：2023-04-18

申请号：US17197482

申请日：2021-03-10

Applicant: Sung Woo Lee ,  Sangho Lee

Inventor： Sung Woo Lee ,  Sangho Lee

IPC: E01D19/12 ,  E01D101/24 ,  E01D101/30

Abstract: A modular paneled structure, comprising a main panel with a symmetric profile which has a closed-sectional portion in the middle and open-sectional portions at each end; and further comprising a cover panel which interconnects two side-by-side main panels, where the cover panel closes the open-sectional portions of the two side-by-side main panels forming a closed-sectional shape together with main panels; and further comprising a tensioning member which interconnects and pre-tensions the main panels that are placed side by side; and consequently, forms an assembled paneled structure with all these connective means, which is used to construct a paneled ground structures.

公开(公告)号：US20210332539A1

公开(公告)日：2021-10-28

申请号：US17197482

申请日：2021-03-10

Applicant: Sung Woo LEE ,  Sangho LEE

Inventor： Sung Woo LEE ,  Sangho LEE

IPC: E01D19/12

Abstract: A modular paneled structure, comprising a main panel with a symmetric profile which has a closed-sectional portion in the middle and open-sectional portions at each end; and further comprising a cover panel which interconnects two side-by-side main panels, where the cover panel closes the open-sectional portions of the two side-by-side main panels forming a closed-sectional shape together with main panels; and further comprising a tensioning member which interconnects and pre-tensions the main panels that are placed side by side; and consequently, forms an assembled paneled structure with all these connective means, which is used to construct a paneled ground structures.

公开(公告)号：USD651008S1

公开(公告)日：2011-12-27

申请号：US29383678

申请日：2011-01-20

Applicant: Sangho Lee

Designer： Sangho Lee

公开(公告)号：US20080280422A1

公开(公告)日：2008-11-13

申请号：US11745045

申请日：2007-05-07

Applicant: Junghoon Shin ,  Sangho Lee ,  Sungyoon Lee

Inventor： Junghoon Shin ,  Sangho Lee ,  Sungyoon Lee

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond with a peripheral edge or a corner of the die. The second solder bump provides standoff height physical support to the die.

Abstract translation: 支撑模具的系统包括基板。 在衬底上设置阻焊剂。 第一焊料凸点设置在阻焊剂中以提供通过阻焊剂到衬底的电连接。 在阻焊剂上形成第二焊料凸块，以对应于模具的周边边缘或拐角。 第二个焊料凸块提供了对模具的支座高度物理支撑。

公开(公告)号：US06395578B1

公开(公告)日：2002-05-28

申请号：US09574541

申请日：2000-05-19

Applicant: WonSun Shin ,  DoSung Chun ,  SangHo Lee ,  SeonGoo Lee ,  Vincent DiCaprio

Inventor： WonSun Shin ,  DoSung Chun ,  SangHo Lee ,  SeonGoo Lee ,  Vincent DiCaprio

IPC: H01L2144

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2223/54473 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00012

Abstract: Semiconductor packages having a thin structure capable of easily discharging heat from a semiconductor chip included therein, and methods for fabricating such semiconductor packages, are disclosed. An embodiment of a semiconductor package includes a semiconductor chip having a first major surface and a second major surface, the semiconductor chip being provided at the second major surface with a plurality of input/output pads; a circuit board including a resin substrate having a first major surface and a second major surface, a first circuit pattern formed at the first major surface and provided with a plurality of ball lands, a second circuit pattern formed at the second major surface and provided with a plurality of bond fingers connected with he ball lands by conductive via holes through the resin substrate, cover coats respectively coating the first and second circuit patterns while allowing the bond fingers and the ball lands to be exposed therethrough, and a central through hole adapted to receive the semiconductor chip therein; electrical conductors that electrically connect the input/output pads of the semiconductor chip with the bond fingers of the circuit board, respectively; a resin encapsulate that covers the semiconductor chip, the electrical conductors, and at least part of the circuit board; and, a plurality of conductive balls fused on the ball lands of the circuit board, respectively.

Abstract translation: 公开了具有能够容易地从包括在其中的半导体芯片放出热的薄结构的半导体封装以及制造这种半导体封装的方法。 半导体封装的实施例包括具有第一主表面和第二主表面的半导体芯片，所述半导体芯片在第二主表面处设置有多个输入/输出焊盘; 包括具有第一主表面和第二主表面的树脂基板的电路板，形成在第一主表面处并设置有多个球接头的第一电路图案，形成在第二主表面处并且设置有第二主表面的第二电路图案 通过导电通孔与树皮基板连接的多个粘结指状物，分别涂覆第一和第二电路图案的盖涂层，同时允许粘合指状物和球状区域暴露于其中;以及中心通孔，其适于 在其中接收半导体芯片; 电导体，其将半导体芯片的输入/输出焊盘电连接到电路板的键合指; 覆盖半导体芯片，电导体和电路板的至少一部分的树脂封装; 以及多个导电球分别熔合在电路板的球面上。

公开(公告)号：US08704366B2

公开(公告)日：2014-04-22

申请号：US12911592

申请日：2010-10-25

Applicant: Junghoon Shin ,  Sangho Lee ,  Sungyoon Lee

Inventor： Junghoon Shin ,  Sangho Lee ,  Sungyoon Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/78 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor device includes a wafer and a dicing saw tape that is laminated to a back surface of the wafer. An active surface of the wafer is opposite the back surface of the wafer. The semiconductor device further includes a lamination tape disposed in contact with the wafer. The lamination tape includes an under-film layer contacting the active surface of the wafer. The lamination tape further includes an adhesive layer contacting the under-film layer.

Abstract translation: 半导体器件包括层叠到晶片的背面的晶片和切割锯带。 晶片的活性表面与晶片的背面相对。 半导体器件还包括与晶片接触设置的层压带。 层压带包括与晶片的活性表面接触的底膜层。 层压带还包括与底膜层接触的粘合剂层。

公开(公告)号：USD650604S1

公开(公告)日：2011-12-20

申请号：US29383680

申请日：2011-01-20

Applicant: Sangho Lee

Designer： Sangho Lee