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11.发明授权公开(公告)号：US09030186B2
公开(公告)日：2015-05-12
申请号：US13547042
申请日：2012-07-12
CPC分类号： G05F3/30 , Y10S323/901
摘要： A bandgap voltage reference and voltage regulator system includes a bandgap voltage reference circuit and a voltage regulator circuit that share a single, common amplifier. The amplifier acts as a gain stage for the reference circuit and as an error amplifier for a driver stage of the regulator circuit. The regulator circuit has an input reference generated by the reference circuit, and the reference circuit acts as a load to the driver stage, obviating the need for a bias resistance network. By sharing the amplifier and obviating the need for a resistance network, the area and overall quiescent current of the system are reduced. The system can be implemented in CMOS/BiCMOS technology and is suited for low power applications.
摘要翻译： 带隙电压参考和电压调节器系统包括带隙电压参考电路和共享单个公共放大器的电压调节器电路。 该放大器用作参考电路的增益级，并用作调节器电路的驱动级的误差放大器。 调节器电路具有由参考电路产生的输入参考，并且参考电路充当驱动器级的负载，从而避免了对偏置电阻网络的需要。 通过共享放大器和消除对电阻网络的需求，系统的面积和整体静态电流降低。 该系统可以采用CMOS / BiCMOS技术实现，适用于低功耗应用。
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公开(公告)号：US08803619B1
公开(公告)日：2014-08-12
申请号：US13753544
申请日：2013-01-30
CPC分类号： H03K3/0231
摘要： A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.
摘要翻译： 用于产生输出时钟信号的放大振荡器包括RC电路，自偏置比较器级和逻辑电路。 RC电路产生提供给自偏置比较器级的第一和第二比较器输入信号。 自偏置比较器级包括第一和第二输入级和电压参考电路。 第一和第二输入级中的每一个结合电压参考电路分别形成比较器，即分别对应于第一和第二输入级的第一和第二比较器。 自偏置比较器级基于第一和第二比较器输入信号产生第一和第二比较器输出信号。 第一和第二比较器输出信号被提供给产生输出时钟信号的逻辑电路。
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公开(公告)号：US20140139201A1
公开(公告)日：2014-05-22
申请号：US13681956
申请日：2012-11-20
IPC分类号： G05F3/02
CPC分类号： G05F3/02 , G01R19/16552 , G06F1/28
摘要： Systems and methods for low-power voltage tamper detection are described. In some embodiments, an integrated circuit may include source-follower circuitry configured to produce a scaled down supply voltage. The integrated circuit may also include undervoltage detection circuitry coupled to the source-follower circuitry, the undervoltage detection circuitry configured to output a first signal having a first logic value if the scaled down supply voltage is greater than a low threshold voltage or a second logic value if the scaled down supply voltage is smaller than the low threshold voltage. Additionally or alternatively, the integrated circuit may include overvoltage detection circuitry coupled to the source-follower circuitry, the overvoltage detection circuitry configured to output a second signal having the first logic value if the scaled down supply voltage is smaller than a high threshold voltage or the second logic value if the scaled down supply voltage is greater than the high threshold voltage.
摘要翻译： 描述了用于低功率电压篡改检测的系统和方法。 在一些实施例中，集成电路可以包括被配置为产生按比例缩小的电源电压的源跟随器电路。 集成电路还可以包括耦合到源跟随器电路的欠压检测电路，欠压检测电路被配置为如果按比例缩小的电源电压大于低阈值电压或第二逻辑值，则输出具有第一逻辑值的第一信号 如果按比例缩小的电源电压小于低阈值电压。 附加地或替代地，集成电路可以包括耦合到源极跟随器电路的过电压检测电路，该过电压检测电路被配置为如果按比例缩小的电源电压小于高阈值电压，则输出具有第一逻辑值的第二信号，或者 如果按比例缩小的电源电压大于高阈值电压，则为第二逻辑值。
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公开(公告)号：US20120033772A1
公开(公告)日：2012-02-09
申请号：US12852513
申请日：2010-08-08
申请人： Manish AGGARWAL , Sanjay K. WADHWA
发明人： Manish AGGARWAL , Sanjay K. WADHWA
IPC分类号： H04L7/04
CPC分类号： H04L7/00 , H04L7/0045
摘要： A synchronizer circuit and method for transferring data between mutually asynchronous source and destination clock domains. An input synchronizer cell clocked at an input clock frequency receives input data from the source domain and produces a corresponding intermediate signal. A frequency divider produces a divided clock signal whose frequency is equal to the input clock frequency divided by an integer. An output synchronizer module comprises first and second cascaded synchronizer cells clocked at the divided clock frequency, receives the intermediate signal and produces a corresponding output signal for the destination clock domain.
摘要翻译： 用于在相互异步的源和时钟域之间传送数据的同步器电路和方法。 以输入时钟频率计时的输入同步器单元从源极域接收输入数据并产生相应的中间信号。 分频器产生频率等于输入时钟频率除以整数的分频时钟信号。 输出同步器模块包括以分频时钟频率计时的第一和第二级联同步器单元，接收中间信号并产生用于目的地时钟域的相应输出信号。
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公开(公告)号：US20110215849A1
公开(公告)日：2011-09-08
申请号：US13109013
申请日：2011-05-17
申请人： Sanjay K. Wadhwa , Krishna Thakur
发明人： Sanjay K. Wadhwa , Krishna Thakur
IPC分类号： H03L7/06
CPC分类号： H03L7/0896
摘要： A charge pump includes a charge pump core circuit having a first current source transistor, a second current source transistor and an output terminal (64), and a replica bias circuit. The replica bias circuit has a first reference current source transistor, a second reference current source transistor and a reference node corresponding to the output terminal of the charge pump core circuit. The reference node is connected to gates of the second current source transistor and the second reference current source transistor. A first input of a regulator circuit is connected to the output terminal of the charge pump core circuit. A second input of the regulator circuit is connected to the reference node of the replica bias circuit. An output of the regulator circuit (54) is connected to gates of the first current source transistor and the first reference current source transistor.
摘要翻译： 电荷泵包括具有第一电流源晶体管，第二电流源晶体管和输出端子（64）的电荷泵芯电路和复制偏置电路。 复制偏置电路具有第一参考电流源晶体管，第二参考电流源晶体管和对应于电荷泵芯电路的输出端的参考节点。 参考节点连接到第二电流源晶体管和第二参考电流源晶体管的栅极。 调节器电路的第一输入端连接到电荷泵芯电路的输出端。 调节器电路的第二输入连接到复制偏置电路的参考节点。 调节器电路（54）的输出端连接到第一电流源晶体管和第一参考电流源晶体管的栅极。
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公开(公告)号：US07965129B1
公开(公告)日：2011-06-21
申请号：US12687849
申请日：2010-01-14
IPC分类号： G05F1/10
CPC分类号： G05F1/463
摘要： A temperature compensated current reference circuit has a differential amplifier and a first feedback transistor with a gate coupled to the differential amplifier output. The first feedback transistor couples a supply voltage line to an inverting input of the differential amplifier. There is also a second feedback transistor with a gate coupled to the differential amplifier output, which couples the supply voltage line to a non-inverting input of the differential amplifier. A first temperature dependent conductor couples the inverting input to ground. A primary reference resistor and a second temperature dependent conductor are connected in series and couple the non-inverting input to ground. An output current control transistor has a gate and one other electrode coupled together and a third electrode coupled to the supply voltage line. A secondary reference resistor and a conductivity change sensing transistor are connected in series and couple the gate of the output current control transistor to ground. The conductivity change sensing transistor has a gate coupled to the second one of the two differential inputs. There is a temperature compensation current reference output circuit that has a current reference transistor, an input coupled to the differential amplifier output and another input is coupled to the gate of the output current control transistor.
摘要翻译： 温度补偿电流参考电路具有差分放大器和具有耦合到差分放大器输出的栅极的第一反馈晶体管。 第一反馈晶体管将电源电压线耦合到差分放大器的反相输入端。 还有一个第二反馈晶体管，其栅极耦合到差分放大器输出，其将电源电压线耦合到差分放大器的非反相输入端。 第一温度依赖导体将反相输入端接地。 主参考电阻和第二温度相关导体串联连接，并将非反相输入耦合到地。 输出电流控制晶体管具有耦合在一起的栅极和另一个电极以及耦合到电源电压线的第三电极。 二次参考电阻和电导率变化感测晶体管串联连接，并将输出电流控制晶体管的栅极耦合到地。 电导率变化感测晶体管具有耦合到两个差分输入中的第二个的栅极。 具有温度补偿电流基准输出电路，其具有电流参考晶体管，耦合到差分放大器输出的输入端和另一输入端耦合到输出电流控制晶体管的栅极。
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公开(公告)号：US07495465B2
公开(公告)日：2009-02-24
申请号：US11490441
申请日：2006-07-20
IPC分类号： H03K19/00 , H03K17/16 , H03K19/003 , G06K5/04 , G11B5/00 , G11B20/20 , G06F11/00 , G06F11/30 , G01R31/28 , G08C25/00 , H03M13/00 , H04L1/00
CPC分类号： H03K19/00384
摘要： A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.
摘要翻译： 补偿电路和补偿包含功能模块的集成电路中的工艺，电压和温度（PVT）变化的方法。 补偿电路包括信号发生器，第一代码发生器，第二代码生成器和映射模块。 信号发生器分别根据对齐的过程角，电压和温度变化以及偏斜过程角变化产生第一信号和第二信号。 第一代码生成器接收第一信号，并产生第一校准码。 第二代码生成器接收第二信号，并产生第二校准码。 映射模块提供第一和第二校准码，用于分别补偿与功能模块相关联的对准过程角，电压和温度变化以及偏斜的过程角变化。
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公开(公告)号：US07446592B2
公开(公告)日：2008-11-04
申请号：US11490440
申请日：2006-07-20
CPC分类号： H03K19/00384
摘要： A compensation circuit and a method for detecting and compensating for process, voltage, and temperature (PVT) variations in an integrated circuit. The integrated circuit includes plural logic modules that include PMOS transistors and NMOS transistors. The compensation circuit includes first and second functional modules, which generate first and second calibration signals. The first and the second calibration signals are used to compensate for the PVT variations in PMOS and NMOS transistors.
摘要翻译： 一种用于检测和补偿集成电路中的过程，电压和温度（PVT）变化的补偿电路和方法。 集成电路包括包括PMOS晶体管和NMOS晶体管的多个逻辑模块。 补偿电路包括产生第一和第二校准信号的第一和第二功能模块。 第一和第二校准信号用于补偿PMOS和NMOS晶体管中的PVT变化。
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公开(公告)号：US07132863B2
公开(公告)日：2006-11-07
申请号：US11098107
申请日：2005-04-04
IPC分类号： H03B19/00
CPC分类号： H03K5/00006
摘要： A digital clock frequency doubler for increasing an input frequency of an input clock signal includes an input block, and a generator block. The input block receives the input clock signal, and generates a pulse signal having an ON period equal to the input clock signal period. The generator block is coupled to the input block. The generator block receives the pulse signal and divides a period of the pulse signal by a period of a high frequency digital signal and then generates an output clock signal with an output frequency that is about two times the input frequency.
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20.发明申请CAPACITOR CHARGING CIRCUIT WITH LOW SUB-THRESHOLD TRANSISTOR LEAKAGE CURRENT 有权具有低子阈值晶体管漏电流的电容器充电电路公开(公告)号：US20140197806A1
公开(公告)日：2014-07-17
申请号：US13743323
申请日：2013-01-16
IPC分类号： H02J7/00
CPC分类号： H03K4/06
摘要： A capacitor charging circuit has input, output and control nodes, first and second series connected primary FETs, and first and second leakage current reduction FETs. All of the FETs have their gates coupled to the control node. The first primary FET is coupled between the input and output nodes, and the second primary FET is coupled between the output node and a leakage current reduction node. The first leakage current reduction FET is coupled between a supply line and the leakage current reduction node, and the second leakage current reduction FET is coupled between the leakage current reduction node and ground. When a control signal at the control node is low, the first primary FET and the first leakage current reduction FET are conductive, and the second primary FET and the second leakage current reduction FET are non-conductive, which eliminates sub-threshold leakage current flowing through the second primary FET.
摘要翻译： 电容充电电路具有输入，输出和控制节点，第一和第二串联连接的主要FET以及第一和第二漏电流减少FET。 所有的FET都具有耦合到控制节点的门。 第一主FET耦合在输入和输出节点之间，第二主要FET耦合在输出节点和漏电流减少节点之间。 第一泄漏电流降低FET耦合在电源线和漏电流减小节点之间，并且第二漏电流减小FET耦合在漏电流减少节点和地之间。 当控制节点处的控制信号为低电平时，第一初级FET和第一漏电流降低FET导通，并且第二初级FET和第二漏电流减小FET不导通，这消除了亚阈值漏电流流动 通过第二个主要FET。
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