公开(公告)号：US07678625B2

公开(公告)日：2010-03-16

申请号：US11962742

申请日：2007-12-21

申请人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

发明人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

IPC分类号： H01L21/84

CPC分类号： H01L21/02675 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/78

摘要： A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.

摘要翻译： 制造包括沟道层的半导体器件的方法包括在半导体衬底上形成单晶半导体层。 单晶半导体层包括从其表面延伸的突起。 在单晶半导体层上执行第一抛光工艺以去除突起的一部分，使得单晶半导体层包括突起的剩余部分。 执行与第一抛光工艺不同的第二抛光工艺以去除突起的剩余部分并限定具有基本上均匀厚度的基本上平面的单晶半导体层。 可以在单晶半导体层上形成牺牲层，并且用作第一抛光工艺的抛光止挡件以限定可在第二抛光工艺之前去除的牺牲层图案。 还讨论了制造叠层半导体存储器件的相关方法。

公开(公告)号：US20150214289A1

公开(公告)日：2015-07-30

申请号：US14509828

申请日：2014-10-08

申请人： Chan-Won Kim ,  Jung-Woo Seo ,  Kee-Hong Lee ,  Kyoung-Ryul Yoon ,  Seong-Kyu Yun

发明人： Chan-Won Kim ,  Jung-Woo Seo ,  Kee-Hong Lee ,  Kyoung-Ryul Yoon ,  Seong-Kyu Yun

IPC分类号： H01L49/02 ,  H01L21/311

CPC分类号： H01L21/311 ,  H01L21/31116 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L28/90

摘要： Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding layer. A second molding layer can be formed on the first molding layer so that the first hole is retained in the first molding layer and a second hole can be formed through the second molding layer to connect with the first hole. A capacitor electrode can be formed in the first and second holes.

摘要翻译： 形成半导体器件的方法可以通过在基片上形成第一成型层并通过第一成型层形成第一孔来提供。 可以在第一成型层上形成第二成型层，使得第一孔保持在第一成型层中，并且可以通过第二成型层形成第二孔以与第一孔连接。 可以在第一和第二孔中形成电容器电极。

公开(公告)号：US08470663B2

公开(公告)日：2013-06-25

申请号：US13048683

申请日：2011-03-15

申请人： Seong-Kyu Yun ,  Jae-Seok Kim

发明人： Seong-Kyu Yun ,  Jae-Seok Kim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/31053 ,  H01L21/823814 ,  H01L21/823828 ,  H01L23/544 ,  H01L29/7848 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is formed on the integrated structures. A first polishing of the first preliminary insulating interlayer is performed until at least one upper surface of the hard mask patterns is exposed, to form a second preliminary insulating interlayer. The second preliminary insulating interlayer is etched until the upper surfaces of the hard mask patterns are exposed, to form a third preliminary insulating interlayer. A second polishing of the hard mask patterns and the third preliminary insulating interlayer is performed until the polysilicon patterns are exposed to form an insulating interlayer. The polysilicon patterns are removed to form an opening. A metal material is deposed to form a gate electrode pattern in the opening.

摘要翻译： 制造半导体器件的方法包括在分成至少NMOS形成区域和PMOS形成区域的衬底上形成多晶硅图案和硬掩模图案的集成结构。 在集成结构上形成第一初步绝缘中间层。 执行第一初步绝缘中间层的第一次抛光，直到暴露硬掩模图案的至少一个上表面，以形成第二预绝缘中间层。 蚀刻第二初步绝缘中间层直到硬掩模图案的上表面露出，以形成第三初步绝缘中间层。 执行硬掩模图案和第三预备绝缘中间层的第二次抛光，直到多晶硅图案暴露以形成绝缘中间层。 去除多晶硅图形以形成开口。 金属材料被放弃以在开口中形成栅极电极图案。

公开(公告)号：US07846801B2

公开(公告)日：2010-12-07

申请号：US11833050

申请日：2007-08-02

申请人： Sung-jun Kim ,  Seong-kyu Yun ,  Chang-ki Hong ,  Bo-un Yoon ,  Jong-won Lee ,  Ho-young Kim

发明人： Sung-jun Kim ,  Seong-kyu Yun ,  Chang-ki Hong ,  Bo-un Yoon ,  Jong-won Lee ,  Ho-young Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.

摘要翻译： 公开了一种制造包括多栅极晶体管的半导体器件的方法。 制造半导体器件的方法包括提供具有多个沿第一方向延伸的活性图案的半导体器件，被隔离层隔开并被第一绝缘层覆盖; 通过在第一方向上蚀刻位于彼此相邻的有源图案之间的隔离层来形成第一凹槽; 用钝化层掩埋第一槽; 通过在与所述第一方向相交的第二方向上蚀刻位于所述有源图案之间的所述隔离层来形成暴露所述有源图案的两侧的至少一部分的第二凹槽; 去除第一凹槽中的钝化层; 以及形成填充所述第二凹槽的至少一部分并沿所述第二方向延伸的栅极线。

公开(公告)号：US20080164503A1

公开(公告)日：2008-07-10

申请号：US11970770

申请日：2008-01-08

申请人： Suk-Hun Choi ,  Chang-Ki Hong ,  Jung-Hyeon Kim ,  Jun-Young Lee ,  Jong-Heun Lim ,  Seong-Kyu Yun

发明人： Suk-Hun Choi ,  Chang-Ki Hong ,  Jung-Hyeon Kim ,  Jun-Young Lee ,  Jong-Heun Lim ,  Seong-Kyu Yun

IPC分类号： G11C11/22 ,  H01L29/78 ,  H01L21/02

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/82

摘要： A ferroelectric memory device and methods of forming the same are provided. Forming a ferroelectric device includes forming an insulation layer over a substrate having a conductive region, forming a bottom electrode electrically connected to the conductive region in the insulation layer, recessing the insulation layer, and forming a ferroelectric layer and an upper electrode layer covering the bottom electrode over the recessed insulation layer, The bottom electrode protrudes over an upper surface of the recessed insulation layer.

摘要翻译： 提供了铁电存储器件及其形成方法。 形成铁电体器件包括在具有导电区域的衬底上形成绝缘层，形成与绝缘层中的导电区域电连接的底部电极，使绝缘层凹陷，并形成覆盖底部的铁电层和上电极层 电极在凹陷绝缘层上方，底部电极突出在凹陷绝缘层的上表面上。

公开(公告)号：US20080045019A1

公开(公告)日：2008-02-21

申请号：US11833050

申请日：2007-08-02

申请人： Sung-jun Kim ,  Seong-kyu Yun ,  Chang-ki Hong ,  Bo-un Yoon ,  Jong-won Lee ,  Ho-young Kim

发明人： Sung-jun Kim ,  Seong-kyu Yun ,  Chang-ki Hong ,  Bo-un Yoon ,  Jong-won Lee ,  Ho-young Kim

IPC分类号： H01L21/302

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.

摘要翻译： 公开了一种制造包括多栅极晶体管的半导体器件的方法。 制造半导体器件的方法包括提供具有多个沿第一方向延伸的活性图案的半导体器件，被隔离层隔开并被第一绝缘层覆盖; 通过在第一方向上蚀刻位于彼此相邻的有源图案之间的隔离层来形成第一凹槽; 用钝化层掩埋第一槽; 通过在与所述第一方向相交的第二方向上蚀刻位于所述有源图案之间的所述隔离层来形成暴露所述有源图案的两侧的至少一部分的第二凹槽; 去除第一凹槽中的钝化层; 以及形成填充所述第二凹槽的至少一部分并沿所述第二方向延伸的栅极线。