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    Semiconductor device and gate structure having a composite dielectric layer and methods of manufacturing the same
    1.
    发明申请
    Semiconductor device and gate structure having a composite dielectric layer and methods of manufacturing the same 有权
    具有复合介质层的半导体器件和栅极结构及其制造方法

    公开(公告)号：US20090250741A1

    公开(公告)日：2009-10-08

    申请号：US12457364

    申请日：2009-06-09

    申请人： Ki-Yeon Park ,  Kyoung-Ryul Yoon ,  Dae-Sik Choi ,  Han-Mei Choi ,  Seung-Hwan Lee

    发明人： Ki-Yeon Park ,  Kyoung-Ryul Yoon ,  Dae-Sik Choi ,  Han-Mei Choi ,  Seung-Hwan Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L21/022 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02247 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/318 ,  H01L29/513 ,  H01L29/7881

    摘要： A semiconductor device and/or gate structure having a composite dielectric layer and methods of manufacturing the same is provided. In the semiconductor device, gate structure, and methods provided, a first conductive layer may be formed on a substrate. A native oxide layer formed on the first conductive layer may be removed. A surface of the first conductive layer may be nitrided so that the surface may be altered into a nitride layer. A composite dielectric layer including the first and/or second dielectric layers may be formed on the nitride layer. A second conductive layer may be formed on the composite dielectric layer. The first dielectric layer may include a material having a higher dielectric constant. The second dielectric layer may be capable of suppressing crystallization of the first dielectric layer.

    摘要翻译： 提供了具有复合电介质层的半导体器件和/或栅极结构及其制造方法。 在半导体器件中，提供栅极结构和方法，可以在衬底上形成第一导电层。 可以除去形成在第一导电层上的自然氧化物层。 第一导电层的表面可以被氮化，使得表面可以改变为氮化物层。 可以在氮化物层上形成包括第一和/或第二电介质层的复合电介质层。 可以在复合介电层上形成第二导电层。 第一电介质层可以包括具有较高介电常数的材料。 第二电介质层可以抑制第一电介质层的结晶化。

    Gate structures of a non-volatile memory device and methods of manufacturing the same
    4.
    发明申请
    Gate structures of a non-volatile memory device and methods of manufacturing the same 有权
    非易失性存储器件的门结构及其制造方法

    公开(公告)号：US20060220106A1

    公开(公告)日：2006-10-05

    申请号：US11375762

    申请日：2006-03-15

    申请人： Han-Mei Choi ,  Kyoung-Ryul Yoon ,  Seung-Hwan Lee ,  Ki-Yeon Park ,  Young-Sun Kim

    发明人： Han-Mei Choi ,  Kyoung-Ryul Yoon ,  Seung-Hwan Lee ,  Ki-Yeon Park ,  Young-Sun Kim

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L29/513

    摘要： In a gate structure of a non-volatile memory device is formed, a tunnel insulating layer and a charge trapping layer are formed on a substrate. A composite dielectric layer is formed on the charge trapping layer and has a laminate structure in which first material layers including aluminum oxide and second material layers including hafnium oxide or zirconium oxide are alternately stacked. A conductive layer is formed on the composite dielectric layer and then a gate structure is formed by patterning the conductive layer, the composite dielectric layer, the charge trapping layer, and the tunnel insulating layer.

    摘要翻译： 在形成非易失性存储器件的栅极结构中，在衬底上形成隧道绝缘层和电荷俘获层。 在电荷捕获层上形成复合电介质层，并且具有层叠结构，其中包括氧化铝的第一材料层和包括氧化铪或氧化锆的第二材料层交替堆叠。 在复合电介质层上形成导电层，然后通过图案化导电层，复合介电层，电荷俘获层和隧道绝缘层形成栅极结构。

    Method of forming a semiconductor memory device
    7.
    发明授权
    Method of forming a semiconductor memory device 有权
    形成半导体存储器件的方法

    公开(公告)号：US08772167B2

    公开(公告)日：2014-07-08

    申请号：US13587996

    申请日：2012-08-17

    申请人： JungWoo Seo ,  Kyoung Ryul Yoon ,  Kukhan Yoon

    发明人： JungWoo Seo ,  Kyoung Ryul Yoon ,  Kukhan Yoon

    IPC分类号： H01L21/311

    CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/91

    摘要： A method of forming a semiconductor memory device includes forming an etch target layer on a substrate, forming a sacrificial layer having preliminary openings on the etch target layer, forming assistance spacers in the preliminary openings, respectively, removing the sacrificial layer, such that the assistance spacers remain on the etch target layer, forming first mask spacers covering inner sidewalls of the assistance spacers, respectively, the first mask spacers respectively defining first openings, forming a second mask spacer covering outer sidewalls of the assistance spacers, the second mask spacer defining second openings between the first openings, the first and second openings being adjacent to each other along a first direction, and etching the etch target layer exposed by the first openings and the second openings to form holes in the etch target layer.

    摘要翻译： 一种形成半导体存储器件的方法包括在衬底上形成蚀刻目标层，在蚀刻目标层上形成具有预备开口的牺牲层，分别在预备开口中形成辅助间隔物，去除牺牲层，使得辅助 间隔物保留在蚀刻目标层上，分别形成覆盖辅助间隔物的内侧壁的第一掩模间隔物，第一掩模间隔物分别限定第一开口，形成覆盖辅助间隔物的外侧壁的第二掩模间隔物，第二掩模间隔物限定第二 第一开口之间的开口，第一和第二开口沿着第一方向彼此相邻，并蚀刻由第一开口和第二开口暴露的蚀刻目标层，以在蚀刻目标层中形成孔。

    Semiconductor device and gate structure having a composite dielectric layer and methods of manufacturing the same
    8.
    发明授权
    Semiconductor device and gate structure having a composite dielectric layer and methods of manufacturing the same 有权
    具有复合介质层的半导体器件和栅极结构及其制造方法

    公开(公告)号：US07888727B2

    公开(公告)日：2011-02-15

    申请号：US12457364

    申请日：2009-06-09

    申请人： Ki-Yeon Park ,  Kyoung-Ryul Yoon ,  Dae-Sik Choi ,  Han-Mei Choi ,  Seung-Hwan Lee

    发明人： Ki-Yeon Park ,  Kyoung-Ryul Yoon ,  Dae-Sik Choi ,  Han-Mei Choi ,  Seung-Hwan Lee

    IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L21/022 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02247 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/318 ,  H01L29/513 ,  H01L29/7881

    摘要： A semiconductor device and/or gate structure having a composite dielectric layer and methods of manufacturing the same is provided. In the semiconductor device, gate structure, and methods provided, a first conductive layer may be formed on a substrate. A native oxide layer formed on the first conductive layer may be removed. A surface of the first conductive layer may be nitrided so that the surface may be altered into a nitride layer. A composite dielectric layer including the first and/or second dielectric layers may be formed on the nitride layer. A second conductive layer may be formed on the composite dielectric layer. The first dielectric layer may include a material having a higher dielectric constant. The second dielectric layer may be capable of suppressing crystallization of the first dielectric layer.

    摘要翻译： 提供了具有复合电介质层的半导体器件和/或栅极结构及其制造方法。 在半导体器件中，提供栅极结构和方法，可以在衬底上形成第一导电层。 可以除去形成在第一导电层上的自然氧化物层。 第一导电层的表面可以被氮化，使得表面可以改变为氮化物层。 可以在氮化物层上形成包括第一和/或第二电介质层的复合电介质层。 可以在复合介电层上形成第二导电层。 第一电介质层可以包括具有较高介电常数的材料。 第二电介质层可以抑制第一电介质层的结晶化。