公开(公告)号：US20090262595A1

公开(公告)日：2009-10-22

申请号：US12106931

申请日：2008-04-21

申请人： Thomas KUENEMUND ,  Artur WROBLEWSKI

发明人： Thomas KUENEMUND ,  Artur WROBLEWSKI

IPC分类号： G11C8/10 ,  H04K1/00 ,  G11C8/00

CPC分类号： G11C7/1006 ,  G11C7/1009

摘要： A plurality of masked memory cells organized in at least two groups, each group using an individual mask signal, is operated by providing a logically valid mask signal only for a selected group comprising the memory cell to be accessed while a logically invalid mask signal are used for all groups other than the selected group.

摘要翻译： 通过在使用逻辑无效掩码信号的情况下，仅为包括要访问的存储器单元的所选择的组提供逻辑有效的掩码信号来操作组中至少两组的每个组的多个屏蔽存储单元，每个组使用单独的屏蔽信号 对于所选组以外的所有组。

公开(公告)号：US07477552B2

公开(公告)日：2009-01-13

申请号：US11668214

申请日：2007-01-29

申请人： Josef Haid ,  Thomas Kuenemund ,  Thomas Leutgeb ,  Bernd Zimek

发明人： Josef Haid ,  Thomas Kuenemund ,  Thomas Leutgeb ,  Bernd Zimek

IPC分类号： G11C5/14 ,  G11C11/00

CPC分类号： G11C5/14

摘要： An apparatus for reducing leakage currents of an integrated circuit having at least one transistor, wherein the at least one transistor is connected between a supply potential and a first reference potential, the apparatus including a controller for controlling the first reference potential in dependence on the supply potential.

摘要翻译： 一种用于减少具有至少一个晶体管的集成电路的泄漏电流的装置，其中所述至少一个晶体管连接在电源电势和第一参考电位之间，所述装置包括用于根据供电来控制第一参考电位的控制器 潜在。

公开(公告)号：US20070217277A1

公开(公告)日：2007-09-20

申请号：US11686509

申请日：2007-03-15

申请人： THOMAS KUENEMUND

发明人： THOMAS KUENEMUND

IPC分类号： G11C5/14

CPC分类号： G11C11/419

摘要： The energy consumption of a static memory cell, which may be connected to a first bit line and a second bit line of a bit line pair by means of transistors, is reduced in an energy-saving mode of operation by adjusting the potentials on each of the bit lines of the bit line pair such that a potential difference between the gate terminals of the transistors and the bit lines of the bit line pair is reduced in comparison with a normal mode of operation.

摘要翻译： 可以通过晶体管连接到位线对的第一位线和第二位线的静态存储单元的能量消耗在节能的操作模式中通过调节每个 位线对的位线使得晶体管的栅极端子和位线对的位线之间的电位差与正常工作模式相比减小。

公开(公告)号：US20050146911A1

公开(公告)日：2005-07-07

申请号：US11022278

申请日：2004-12-23

申请人： Thomas Kuenemund

发明人： Thomas Kuenemund

IPC分类号： G11C5/06

CPC分类号： G06F7/00 ,  G06F2207/7223 ,  G06F2207/7266 ,  G11C5/063

摘要： A transmission device has a device for generating a signal pair and a device for generating a recovered data signal. The device for generating the signal pair is formed to output a first data signal either as first signal or as first complementary signal in response to a value of a switching signal. The device for generating a recovered data signal is, in turn, formed to output the first signal as a first recovered data signal or the first complementary signal as the first recovered data signal in response to a value of the switching signal.

摘要翻译： 发送装置具有用于产生信号对的装置和用于产生恢复的数据信号的装置。 用于产生信号对的装置被形成为响应于切换信号的值，将第一数据信号作为第一信号或第一互补信号输出。 用于产生恢复的数据信号的装置又被形成为响应于切换信号的值，将作为第一恢复数据信号或第一互补信号的第一信号作为第一恢复数据信号输出。

公开(公告)号：US5371832A

公开(公告)日：1994-12-06

申请号：US22447

申请日：1993-02-25

申请人： Herbert Eichfeld ,  Thomas Kuenemund

发明人： Herbert Eichfeld ,  Thomas Kuenemund

IPC分类号： G05B13/02 ,  G06N7/04 ,  G06F15/18

CPC分类号： G06N7/04 ,  G05B13/0275 ,  Y10S706/90

摘要： A fuzzy logic controller is composed of a fuzzification circuit (FUZ), a rule decoder (RDEC), a rule evaluation circuit (RA), an inference circuit (INF), a defuzzification circuit (DFUZ) and a sequencer (CTRL). Numbers (NA) for linguistic values of the output variables together with selection signals (SM) for the definition of the input variables affected by the respective rule formed in the rule decoder and are supplied to the rule evaluation circuit in addition to the values (ME) of the affiliation functions for the linguistic values of the input variables. A weighting signal (G) is generated in the rule evaluation circuit for every linguistic value of the output variables. The advantages obtainable are the high processing speed, the low requirement for chip area, the variable rule format and the selection possibility of different operation modes in the rule evaluation circuit, the inference circuit and the defuzzification circuit.

摘要翻译： 模糊逻辑控制器由模糊化电路（FUZ），规则解码器（RDEC），规则评估电路（RA），推理电路（INF），去模糊化电路（DFUZ）和定序器（CTRL）组成。 用于输出变量的语言值的数字（NA）以及由规则解码器中形成的相应规则影响的输入变量的定义的选择信号（SM），并且除了值（ME）之外还提供给规则评估电路 ）输入变量的语言值的隶属函数。 对于输出变量的每个语言值，在规则评估电路中生成加权信号（G）。 可获得的优点是规则评估电路中的处理速度快，芯片面积要求低，可变规则格式和不同工作模式的选择可能性，推理电路和去模糊电路。

公开(公告)号：US08726123B2

公开(公告)日：2014-05-13

申请号：US13548462

申请日：2012-07-13

申请人： Rainer Goettfert ,  Berndt Gammel ,  Thomas Kuenemund

发明人： Rainer Goettfert ,  Berndt Gammel ,  Thomas Kuenemund

IPC分类号： H03M13/00

CPC分类号： G06F11/10 ,  G06F11/1008 ,  G06F21/35 ,  G06F21/72 ,  H03M13/05 ,  H03M13/63 ,  H04L9/0866 ,  H04L2209/34

摘要： A bit error corrector includes an aging bit pattern memory operable to store at least one aging bit pattern which conveys aging-related effects within a succession of uncorrected bit patterns, a bit pattern modifier operable to modify a current, uncorrected bit pattern using the at least one aging bit pattern and generate a modified bit pattern, and a bit pattern comparator operable to compare the current uncorrected bit pattern with a corrected bit pattern which is based on the modified bit pattern and determine a corresponding comparative bit pattern. An aging bit pattern determiner is operable to recursively determine a new aging bit pattern based on the at least one aging bit pattern and the comparative bit pattern, and store the new aging bit pattern in the aging bit pattern memory for use during modification of a subsequent uncorrected bit pattern by the bit pattern modifier.

摘要翻译： 位错误校正器包括老化位模式存储器，其可操作以存储在一系列未校正位模式中传达与老化有关的效应的至少一个老化位模式，位模式修改器可操作以使用至少一个修正的未校正位模式 一个老化比特模式并产生修改的比特模式，以及比特模式比较器，用于将当前未校正比特模式与基于修改的比特模式的校正比特模式进行比较，并确定相应的比较比特模式。 老化位模式确定器可操作以基于至少一个老化位模式和比较位模式递归地确定新的老化位模式，并将新的老化位模式存储在老化位模式存储器中，以在后续修改期间使用 未校正的位模式由位模式修改器。

公开(公告)号：US08334707B2

公开(公告)日：2012-12-18

申请号：US12344916

申请日：2008-12-29

申请人： Thomas Kuenemund

发明人： Thomas Kuenemund

IPC分类号： G06F7/38 ,  G06F7/04 ,  G06F17/30 ,  H03K19/00 ,  H03L7/00

CPC分类号： G11C7/24

摘要： Some embodiments show a storage circuit with fault detection. The storage circuit comprises, first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state. Furthermore the storage circuit comprises a data input, a circuitry configured to cause the first fault detection circuit to assume the first stable state and the second fault detection circuit to assume the second stable state to store a data signal applied to the data input and a first output indicative of the state of the first fault detection circuit and a second output indicative of the state of the second fault detection circuit, wherein an invalid combination of the signal states at the first and second outputs indicate a fault.

摘要翻译： 一些实施例示出了具有故障检测的存储电路。 存储电路包括第一和第二故障检测电路，每个包括第一稳定状态和第二稳定状态，其中第一和第二故障检测电路中的每一个被配置为使得从第一稳定状态引起切换所需的故障信号强度 状态到第二稳定状态不同于使从第二稳定状态切换到第一稳定状态所需的故障信号强度。 此外，存储电路包括数据输入端，被配置为使第一故障检测电路呈现第一稳定状态的电路，而第二故障检测电路采用第二稳定状态以存储施加到数据输入端的数据信号;以及第一 输出表示第一故障检测电路的状态的第二输出和指示第二故障检测电路的状态的第二输出，其中在第一和第二输出处的信号状态的无效组合指示故障。

公开(公告)号：US08135767B2

公开(公告)日：2012-03-13

申请号：US11890966

申请日：2007-08-08

申请人： Thomas Kuenemund

发明人： Thomas Kuenemund

IPC分类号： G06F7/38 ,  G06F7/52

CPC分类号： G06F7/5016 ,  G06F7/764

摘要： A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.

摘要翻译： 用于算术逻辑单元的单元包括第一输入; 第二个输入 输入输入; 第一控制输入和第二控制输入; 以及连接到第一输入端，第二输入端，进位输入端，第一控制输入端和第二控制输入端的电路。 该电路具有第一输出和第二输出，当第一控制输入和第二控制输入的值等于进位时的值时，第二输出具有作为第一输入和第二输入的函数的第一值， 并且当第一控制输入和第二控制输入处的值与进位输入处的值无关时具有作为第一输入和第二输入的函数的第二值。

公开(公告)号：US08130008B2

公开(公告)日：2012-03-06

申请号：US12714678

申请日：2010-03-01

申请人： Thomas Kuenemund

发明人： Thomas Kuenemund

IPC分类号： G01R31/02

CPC分类号： H03K17/72 ,  G06F21/81 ,  G06F21/87 ,  H01L23/576 ,  H01L31/1113 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit comprises a circuit used for storing or processing data and a radiation-sensitive thyristor structure configured to conditionally short two power supply terminals of the integrated circuit. The thyristor structure is configured to turn on in response to a region of the thyristor structure being irradiated with radiation to which the thyristor structure is sensitive, in order to establish an electrically conductive connection between a first power supply terminal of the power supply terminals of the integrated circuit and a second power supply terminal of the power supply terminals of the integrated circuit. The thyristor structure is further configured so that a power density of the radiation needed for turning on the thyristor structure is lower than a power density of the radiation needed for a change of data of the circuit used for storing or processing data.

摘要翻译： 集成电路包括用于存储或处理数据的电路和被配置为有条件地短路集成电路的两个电源端子的辐射敏感晶闸管结构。 晶闸管结构被配置为响应于晶闸管结构的区域被可控硅结构敏感的辐射照射而导通，以便在所述晶闸管结构的电源端子的第一电源端子之间建立导电连接， 集成电路和集成电路的电源端子的第二电源端子。 晶闸管结构被进一步配置，使得用于导通晶闸管结构所需的辐射的功率密度低于用于存储或处理数据的电路的数据变化所需的辐射的功率密度。

公开(公告)号：US20110210782A1

公开(公告)日：2011-09-01

申请号：US12714678

申请日：2010-03-01

申请人： Thomas Kuenemund

发明人： Thomas Kuenemund

IPC分类号： H03K17/74 ,  H05K1/00 ,  G06F21/02 ,  H03K17/78

CPC分类号： H03K17/72 ,  G06F21/81 ,  G06F21/87 ,  H01L23/576 ,  H01L31/1113 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit comprises a circuit used for storing or processing data and a radiation-sensitive thyristor structure configured to conditionally short two power supply terminals of the integrated circuit. The thyristor structure is configured to turn on in response to a region of the thyristor structure being irradiated with radiation to which the thyristor structure is sensitive, in order to establish an electrically conductive connection between a first power supply terminal of the power supply terminals of the integrated circuit and a second power supply terminal of the power supply terminals of the integrated circuit. The thyristor structure is further configured so that a power density of the radiation needed for turning on the thyristor structure is lower than a power density of the radiation needed for a change of data of the circuit used for storing or processing data.

摘要翻译： 集成电路包括用于存储或处理数据的电路和被配置为有条件地短路集成电路的两个电源端子的辐射敏感晶闸管结构。 晶闸管结构被配置为响应于晶闸管结构的区域被可控硅结构敏感的辐射照射而导通，以便在所述晶闸管结构的电源端子的第一电源端子之间建立导电连接， 集成电路和集成电路的电源端子的第二电源端子。 晶闸管结构被进一步配置，使得用于导通晶闸管结构所需的辐射的功率密度低于用于存储或处理数据的电路的数据变化所需的辐射的功率密度。