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    Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage
    11.
    发明授权
    Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage 有权
    评估SOI设计和结构中充电损害潜力的方法，以消除损坏的可能性

    公开(公告)号：US07132318B2

    公开(公告)日：2006-11-07

    申请号：US11003988

    申请日：2004-12-04

    Applicant: Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

    Inventor： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

    IPC: H01L21/00 ,  H01L21/336 ,  H01L21/8234

    CPC classification number: H01L27/0251

    Abstract: Disclosed is a method and structure for altering an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that may have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.

    Abstract translation: 公开了一种用于改变具有绝缘体上硅（SOI）晶体管的集成电路设计的方法和结构。 该方法/结构通过在集成电路设计中跟踪电网来防止在处理到SOI晶体管的栅极期间的充电损坏，识别可能在源极/漏极和栅极之间具有电压差的SOI晶体管作为潜在损坏的SOI晶体管（基于 电网的跟踪），以及在每个潜在损坏的SOI晶体管的源极/漏极和栅极之间连接分流器件。 或者，方法/结构提供通过串联装置连接补偿导体。

    Active pixel sensor cell and method of using
    14.
    发明授权
    Active pixel sensor cell and method of using 失效
    有源像素传感器单元及其使用方法

    公开(公告)号：US6026964A

    公开(公告)日：2000-02-22

    申请号：US920182

    申请日：1997-08-25

    Applicant: Terence B. Hook ,  Jeffrey B. Johnson ,  Hon-Sum P. Wong

    Inventor： Terence B. Hook ,  Jeffrey B. Johnson ,  Hon-Sum P. Wong

    IPC: H01L27/146 ,  H01L31/0352 ,  H01L31/10 ,  H01L31/14 ,  H01L31/062

    CPC classification number: H01L27/14643 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/0352

    Abstract: The present invention is a active pixel sensor cell and method of making and using the same. The active pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a active pixel sensor cell circuit. Two active pixel sensor cell circuits, an NFET circuit and PFET circuit are created for use with a photodiode. The NFET circuit captures electron current. The PFET circuit captures hole current. The sum of the currents is approximately double that of conventional active pixel sensor circuits using similarly sized photodiode regions.

    Abstract translation: 本发明是一种有源像素传感器单元及其制造和使用方法。 有源像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在有源像素传感器单元电路中照射光子而产生的空穴。 创建两个有源像素传感器单元电路，NFET电路和PFET电路用于光电二极管。 NFET电路捕获电子电流。 PFET电路捕获空穴电流。 电流的总和大约是使用类似尺寸的光电二极管区域的传统有源像素传感器电路的总和的两倍。

    Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability
    15.
    发明授权
    Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability 有权
    具有多个阈值电压和有源阱偏置能力的CMOS ETSOI的结构

    公开(公告)号：US08552500B2

    公开(公告)日：2013-10-08

    申请号：US13114283

    申请日：2011-05-24

    Applicant: Robert H. Dennard ,  Terence B. Hook

    Inventor： Robert H. Dennard ,  Terence B. Hook

    IPC: H01L27/12

    CPC classification number: H01L27/1203 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84

    Abstract: A semiconductor substrate having a first type of conductivity and a top surface, a layer of oxide disposed over the top surface and a semiconductor layer disposed over the layer of oxide. A plurality of transistor devices are disposed upon the semiconductor layer. Each transistor device includes a channel between a source and a drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. A well region is formed adjacent to the top surface. The well region has a second type of conductivity. First trench isolation regions are between adjacent transistor devices that extend through the semiconductor layer. Second trench isolation regions are between adjacent transistor devices of opposite channel conductivity.

    Abstract translation: 具有第一导电类型和顶表面的半导体衬底，设置在顶表面上的氧化物层和设置在氧化物层上的半导体层。 多个晶体管器件设置在半导体层上。 每个晶体管器件包括在源极和漏极之间的沟道，其中一些晶体管器件具有第一类型的沟道导电性，并且剩余的晶体管器件具有第二类型的沟道导电性。 阱区域邻近顶表面形成。 阱区具有第二类导电性。 第一沟槽隔离区域在延伸穿过半导体层的相邻晶体管器件之间。 第二沟槽隔离区域在相反的沟道导电性的相邻晶体管器件之间。

    Method and structure for balancing power and performance using fluorine and nitrogen doped substrates
    16.
    发明授权
    Method and structure for balancing power and performance using fluorine and nitrogen doped substrates 有权
    使用氟和氮掺杂衬底平衡功率和性能的方法和结构

    公开(公告)号：US08431955B2

    公开(公告)日：2013-04-30

    申请号：US12840689

    申请日：2010-07-21

    Applicant: Brent A. Anderson ,  Terence B. Hook

    Inventor： Brent A. Anderson ,  Terence B. Hook

    IPC: H01L33/00

    CPC classification number: H01L29/78696 ,  G06F17/505 ,  G06F2217/78 ,  H01L29/4908

    Abstract: Methods and systems evaluate an integrated circuit design for power consumption balance and performance balance, using a computerized device. Based on this process of evaluating the integrated circuit, the methods and systems can identify first sets of integrated circuit transistor structures within the integrated circuit design that need reduced power leakage and second sets of integrated circuit transistor structures that need higher performance to achieve the desired power consumption balance and performance balance. With this, the methods and systems alter the integrated circuit design to include implantation of a first dopant into a substrate before a gate insulator formation for the first sets of integrated circuit transistor structures; and alter the integrated circuit design to include implantation of a second dopant into the substrate before a gate insulator formation for the second sets of integrated circuit transistor structures. The method and system then output the altered integrated circuit design from the computerized device and/or manufactures the device according to the altered integrated circuit design.

    Abstract translation: 方法和系统使用计算机化设备评估功耗平衡和性能平衡的集成电路设计。 基于对集成电路进行评估的方法，该方法和系统可以识别集成电路设计中需要减少功率泄漏的第一组集成电路晶体管结构，并且需要更高性能的第二组集成电路晶体管结构来实现所需功率 消费平衡和业绩平衡。 由此，方法和系统改变了集成电路设计，包括在用于第一组集成电路晶体管结构的栅极绝缘体形成之前将第一掺杂剂注入到衬底中; 并且改变集成电路设计以在第二组集成电路晶体管结构的栅极绝缘体形成之前将第二掺杂剂注入到衬底中。 该方法和系统然后从计算机化设备输出改变的集成电路设计和/或根据改变的集成电路设计制造设备。

    Method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range
    17.
    发明授权
    Method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range 有权
    具有相对较大的阈值电压变化范围的晶体管的方法和结构，以及包含具有这样大的阈值电压变化范围的多个基本相同的晶体管的随机数发生器的方法和结构

    公开(公告)号：US08407656B2

    公开(公告)日：2013-03-26

    申请号：US13167826

    申请日：2011-06-24

    Applicant: Terence B. Hook ,  Jeffrey B. Johnson

    Inventor： Terence B. Hook ,  Jeffrey B. Johnson

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  H01L23/544 ,  H01L29/1083 ,  H01L29/7833 ,  H01L2223/5444 ,  H03K3/84

    Abstract: Disclosed are a design method and structure for a transistor having a relatively large threshold voltage (Vt) variation range due to exacerbated random dopant fluctuation (RDF). Exacerbated RDF and, thereby a relatively large Vt variation range, is achieved through the use of complementary doping in one or more transistor components and/or through lateral dopant non-uniformity between the channel region and any halo regions. Also disclosed are a design method and structure for a random number generator, which incorporates multiple pairs of essentially identical transistors having such a large Vt variation and which relies on Vt mismatch in pairs of those the transistors to generate a multi-bit output (e.g., a unique identifier for a chip or a secret key). By widening the Vt variation range of the transistors in the random number generator, detecting Vt mismatch between transistors becomes more likely and the resulting multi-bit output will be more stable.

    Abstract translation: 公开了由于加剧的随机掺杂剂波动（RDF）而具有相对大的阈值电压（Vt）变化范围的晶体管的设计方法和结构。 通过在一个或多个晶体管组件中使用互补掺杂和/或通过沟道区域和任何晕圈区域之间的横向掺杂剂不均匀性来实现RDF的恶化，从而达到相对较大的Vt变化范围。 还公开了一种用于随机数发生器的设计方法和结构，该方法和结构包括具有如此大的Vt变化的多对基本相同的晶体管，并且其依赖于晶体管对的Vt失配以产生多位输出（例如， 芯片或密钥的唯一标识符）。 通过扩大随机数发生器中的晶体管的Vt变化范围，检测晶体管之间的Vt失配变得更可能，并且所得到的多位输出将更加稳定。

    Integrated circuits comprising resistors having different sheet resistances and methods of fabricating the same
    18.
    发明授权
    Integrated circuits comprising resistors having different sheet resistances and methods of fabricating the same 有权
    包括具有不同薄片电阻的电阻器的集成电路及其制造方法

    公开(公告)号：US07785979B2

    公开(公告)日：2010-08-31

    申请号：US12173407

    申请日：2008-07-15

    Applicant: Roger Allen Booth, Jr. ,  Kangguo Cheng ,  Terence B. Hook

    Inventor： Roger Allen Booth, Jr. ,  Kangguo Cheng ,  Terence B. Hook

    IPC: H01L21/324 ,  H01L21/8238

    CPC classification number: H01L27/0629 ,  H01L28/20

    Abstract: The fabrication of integrated circuits comprising resistors having the same structure but different sheet resistances is disclosed herein. In one embodiment, a method of fabricating an integrated circuit comprises: concurrently forming a first resistor laterally spaced from a second resistor above or within a semiconductor substrate, the first and second resistors comprising a doped semiconductive material; depositing a dopant receiving material across the first and second resistors and the semiconductor substrate; removing the dopant receiving material from upon the first resistor while retaining the dopant receiving material upon the second resistor; and annealing the first and second resistors to cause a first sheet resistance of the first resistor to be different from a second sheet resistance of the second resistor.

    Abstract translation: 本文公开了包括具有相同结构但具有不同薄层电阻的电阻器的集成电路的制造。 在一个实施例中，一种制造集成电路的方法包括：与半导体衬底之上或之内的第二电阻器横向隔开的第一电阻器同时形成，所述第一和第二电阻器包括掺杂的半导体材料; 在第一和第二电阻器和半导体衬底上沉积掺杂剂接收材料; 在所述第一电阻器上移除所述掺杂剂接收材料，同时将所述掺杂剂接收材料保持在所述第二电阻器上; 以及使所述第一和第二电阻器退火以使所述第一电阻器的第一薄层电阻与所述第二电阻器的第二薄层电阻不同。

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