公开(公告)号：US08407656B2

公开(公告)日：2013-03-26

申请号：US13167826

申请日：2011-06-24

Applicant: Terence B. Hook ,  Jeffrey B. Johnson

Inventor： Terence B. Hook ,  Jeffrey B. Johnson

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H01L23/544 ,  H01L29/1083 ,  H01L29/7833 ,  H01L2223/5444 ,  H03K3/84

Abstract: Disclosed are a design method and structure for a transistor having a relatively large threshold voltage (Vt) variation range due to exacerbated random dopant fluctuation (RDF). Exacerbated RDF and, thereby a relatively large Vt variation range, is achieved through the use of complementary doping in one or more transistor components and/or through lateral dopant non-uniformity between the channel region and any halo regions. Also disclosed are a design method and structure for a random number generator, which incorporates multiple pairs of essentially identical transistors having such a large Vt variation and which relies on Vt mismatch in pairs of those the transistors to generate a multi-bit output (e.g., a unique identifier for a chip or a secret key). By widening the Vt variation range of the transistors in the random number generator, detecting Vt mismatch between transistors becomes more likely and the resulting multi-bit output will be more stable.

Abstract translation: 公开了由于加剧的随机掺杂剂波动（RDF）而具有相对大的阈值电压（Vt）变化范围的晶体管的设计方法和结构。 通过在一个或多个晶体管组件中使用互补掺杂和/或通过沟道区域和任何晕圈区域之间的横向掺杂剂不均匀性来实现RDF的恶化，从而达到相对较大的Vt变化范围。 还公开了一种用于随机数发生器的设计方法和结构，该方法和结构包括具有如此大的Vt变化的多对基本相同的晶体管，并且其依赖于晶体管对的Vt失配以产生多位输出（例如， 芯片或密钥的唯一标识符）。 通过扩大随机数发生器中的晶体管的Vt变化范围，检测晶体管之间的Vt失配变得更可能，并且所得到的多位输出将更加稳定。

公开(公告)号：US06278102B1

公开(公告)日：2001-08-21

申请号：US09415642

申请日：1999-10-12

Applicant: Terence B. Hook ,  Jeffrey B. Johnson ,  Robert Leidy ,  Hon-Sum P. Wong

Inventor： Terence B. Hook ,  Jeffrey B. Johnson ,  Robert Leidy ,  Hon-Sum P. Wong

IPC: H01L2700

CPC classification number: H01L27/14609 ,  H01L27/14603

Abstract: A method of detecting electromagnetic radiation with an active pixel sensor photosensitive device having an extremely thin virtual pinning layer formed by inverting semiconductor material at the surface of a photosensitive region. The thin pinning layer improves blue light response. The inverted pinning layer is produced by connecting a negative potential source to a transparent conductive layer, preferably made of indium-tin-oxide positioned over most of the photosensitive region. The conductive layer is insulated from the photosensitive region by a thin insulating layer. Connection to the pinning layer is through a coupling region formed in an area not covered by the conductive and insulating layers. Red light response is improved and the depth of the photosensitive region reduced by creating a strained layer, preferably of germanium silicon, deep within the photosensitive region. The strained layer has a modified bandgap which increases the absorption rate of red light.

Abstract translation: 一种用有源像素传感器感光装置检测电磁辐射的方法，该感光装置具有通过使感光区域的表面处的半导体材料反相而形成的极薄的虚拟钉扎层。 薄钉扎层改善了蓝光响应。 反向钉扎层是通过将负电位源连接到透明导电层而制成的，该透明导电层优选由位于感光区域的大部分上的氧化铟锡制成。 导电层通过薄的绝缘层与感光区域绝缘。 与钉扎层的连接通过形成在未被导电层和绝缘层覆盖的区域中的耦合区域。 通过在感光区域内形成深层的应变层，优选锗硅，可以改善红光响应并降低感光区的深度。 应变层具有改进的带隙，其增加红光的吸收率。

公开(公告)号：US20120326752A1

公开(公告)日：2012-12-27

申请号：US13167826

申请日：2011-06-24

Applicant: Terence B. Hook ,  Jeffrey B. Johnson

Inventor： Terence B. Hook ,  Jeffrey B. Johnson

IPC: H03K5/24 ,  H01L29/78 ,  G06F17/50

CPC classification number: G06F17/5068 ,  H01L23/544 ,  H01L29/1083 ,  H01L29/7833 ,  H01L2223/5444 ,  H03K3/84

Abstract: Disclosed are a design method and structure for a transistor having a relatively large threshold voltage (Vt) variation range due to exacerbated random dopant fluctuation (RDF). Exacerbated RDF and, thereby a relatively large Vt variation range, is achieved through the use of complementary doping in one or more transistor components and/or through lateral dopant non-uniformity between the channel region and any halo regions. Also disclosed are a design method and structure for a random number generator, which incorporates multiple pairs of essentially identical transistors having such a large Vt variation and which relies on Vt mismatch in pairs of those the transistors to generate a multi-bit output (e.g., a unique identifier for a chip or a secret key). By widening the Vt variation range of the transistors in the random number generator, detecting Vt mismatch between transistors becomes more likely and the resulting multi-bit output will be more stable.

Abstract translation: 公开了由于加剧的随机掺杂剂波动（RDF）而具有相对大的阈值电压（Vt）变化范围的晶体管的设计方法和结构。 通过在一个或多个晶体管组件中使用互补掺杂和/或通过沟道区域和任何晕圈区域之间的横向掺杂剂不均匀性来实现RDF的恶化，从而达到相对较大的Vt变化范围。 还公开了一种用于随机数发生器的设计方法和结构，该方法和结构包括具有如此大的Vt变化的多对基本相同的晶体管，并且其依赖于晶体管对的Vt失配以产生多位输出（例如， 芯片或密钥的唯一标识符）。 通过扩大随机数发生器中的晶体管的Vt变化范围，检测晶体管之间的Vt失配变得更可能，并且所得到的多位输出将更加稳定。

公开(公告)号：US07516426B2

公开(公告)日：2009-04-07

申请号：US11561537

申请日：2006-11-20

Applicant: Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

Inventor： Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

IPC: G06F17/50

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L27/0207

Abstract: Methods of improving operational parameters between at least a pair of matched transistors, and a set of transistors, are disclosed. One embodiment of a method includes a method of improving at least one of a threshold voltage (Vt) mismatch and current drive between at least a pair of matched transistors for analog applications, the method comprising: forming at least a pair of transistors, each with a gate having a plurality of connected fingers; and optimizing a total length of a channel under the plurality of fingers to attain at least one of: a) a reduced threshold voltage mismatch between the at least pair of transistors, and b) increased current drive for a given threshold voltage mismatch, between the at least pair of transistors, each finger having a length less than an overall length of the channel.

Abstract translation: 公开了改善至少一对匹配晶体管之间的操作参数的方法和一组晶体管。 方法的一个实施例包括一种改进用于模拟应用的至少一对匹配晶体管之间的阈值电压（Vt）失配和电流驱动中的至少一个的方法，所述方法包括：形成至少一对晶体管，每个晶体管具有 具有多个连接的手指的门; 以及优化所述多个指状物下的通道的总长度以达到以下至少一个：a）所述至少一对晶体管之间的阈值电压失配降低，以及b）对于给定阈值电压失配的增加的电流驱动， 至少一对晶体管，每个手指的长度小于通道的总长度。

公开(公告)号：US6026964A

公开(公告)日：2000-02-22

申请号：US920182

申请日：1997-08-25

Applicant: Terence B. Hook ,  Jeffrey B. Johnson ,  Hon-Sum P. Wong

Inventor： Terence B. Hook ,  Jeffrey B. Johnson ,  Hon-Sum P. Wong

IPC: H01L27/146 ,  H01L31/0352 ,  H01L31/10 ,  H01L31/14 ,  H01L31/062

CPC classification number: H01L27/14643 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/0352

Abstract: The present invention is a active pixel sensor cell and method of making and using the same. The active pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a active pixel sensor cell circuit. Two active pixel sensor cell circuits, an NFET circuit and PFET circuit are created for use with a photodiode. The NFET circuit captures electron current. The PFET circuit captures hole current. The sum of the currents is approximately double that of conventional active pixel sensor circuits using similarly sized photodiode regions.

Abstract translation: 本发明是一种有源像素传感器单元及其制造和使用方法。 有源像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在有源像素传感器单元电路中照射光子而产生的空穴。 创建两个有源像素传感器单元电路，NFET电路和PFET电路用于光电二极管。 NFET电路捕获电子电流。 PFET电路捕获空穴电流。 电流的总和大约是使用类似尺寸的光电二极管区域的传统有源像素传感器电路的总和的两倍。

公开(公告)号：US06194702B1

公开(公告)日：2001-02-27

申请号：US09290755

申请日：1999-04-13

Applicant: Terence B. Hook ,  Jeffrey B. Johnson ,  Hon-Sum P. Wong

Inventor： Terence B. Hook ,  Jeffrey B. Johnson ,  Hon-Sum P. Wong

IPC: H01L3100

CPC classification number: H01L27/14643 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/0352

Abstract: The present invention is a complementary active pixel sensor cell and method of making and using the same. The complementary active pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a complementary active pixel sensor cell circuit. Two active pixel sensor cell circuits, an NFET circuit and complementary PFET circuit are created for use with a photodiode. The NFET circuit captures electron current. The PFET circuit captures hole current. The sum of the currents is approximately double that of conventional active pixel sensor circuits using similarly sized photodiode regions.

Abstract translation: 本发明是补充有源像素传感器单元及其制造和使用方法。 补充有源像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用在互补的有源像素传感器单元电路中照射光子产生的空穴。 创建两个有源像素传感器单元电路，NFET电路和互补PFET电路用于光电二极管。 NFET电路捕获电子电流。 PFET电路捕获空穴电流。 电流的总和大约是使用类似尺寸的光电二极管区域的传统有源像素传感器电路的总和的两倍。

公开(公告)号：US20080116527A1

公开(公告)日：2008-05-22

申请号：US11561537

申请日：2006-11-20

Applicant: Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

Inventor： Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L27/0207

Abstract: Methods of improving operational parameters between at least a pair of matched transistors, and a set of transistors, are disclosed. One embodiment of a method includes a method of improving at least one of a threshold voltage (Vt) mismatch and current drive between at least a pair of matched transistors for analog applications, the method comprising: forming at least a pair of transistors, each with a gate having a plurality of connected fingers; and optimizing a total length of a channel under the plurality of fingers to attain at least one of: a) a reduced threshold voltage mismatch between the at least pair of transistors, and b) increased current drive for a given threshold voltage mismatch, between the at least pair of transistors, each finger having a length less than an overall length of the channel.

Abstract translation: 公开了改善至少一对匹配晶体管之间的操作参数的方法和一组晶体管。 方法的一个实施例包括一种改进用于模拟应用的至少一对匹配晶体管之间的阈值电压（Vt）失配和电流驱动中的至少一个的方法，所述方法包括：形成至少一对晶体管，每个晶体管具有 具有多个连接的手指的门; 以及优化所述多个指状物下的通道的总长度以达到以下至少一个：a）所述至少一对晶体管之间的阈值电压失配降低，以及b）对于给定阈值电压失配的增加的电流驱动， 至少一对晶体管，每个手指的长度小于通道的总长度。

公开(公告)号：US08633096B2

公开(公告)日：2014-01-21

申请号：US12943987

申请日：2010-11-11

Applicant: Brian J. Greene ,  Jeffrey B. Johnson ,  Qingqing Liang ,  Edward P. Maciejewski

Inventor： Brian J. Greene ,  Jeffrey B. Johnson ,  Qingqing Liang ,  Edward P. Maciejewski

IPC: H01L29/72

CPC classification number: H01L29/66477 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/38 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions. A transistor dopant species is introduced in the source and drain regions. An anneal is performed so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.

公开(公告)号：US20130285211A1

公开(公告)日：2013-10-31

申请号：US13455732

申请日：2012-04-25

Applicant: Robert J. Gauthier, JR. ,  Jeffrey B. Johnson ,  Junjun Li

Inventor： Robert J. Gauthier, JR. ,  Jeffrey B. Johnson ,  Junjun Li

IPC: H01L29/00 ,  G06F17/50 ,  H01L21/20

CPC classification number: H01L27/1211 ,  G06F17/5068 ,  H01L21/3086 ,  H01L21/845

Abstract: Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.

Abstract translation: 鳍式场效应晶体管集成电路技术的器件结构，设计结构和制造方法。 构成器件结构的电极的第一和第二鳍片均由第一半导体材料构成。 第二翅片邻近第一翅片形成以限定分隔第一和第二翅片的间隙。 位于间隙中的是由第二半导体材料构成的层。

公开(公告)号：US08569810B2

公开(公告)日：2013-10-29

申请号：US12961553

申请日：2010-12-07

Applicant: Jian Yu ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Chengwen Pei ,  Michael Hargrove

Inventor： Jian Yu ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Chengwen Pei ,  Michael Hargrove

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66477 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.