公开(公告)号：US06534348B1

公开(公告)日：2003-03-18

申请号：US09292063

申请日：1999-04-14

Applicant: Theodore S. Moise ,  Glen D. Wilk

Inventor： Theodore S. Moise ,  Glen D. Wilk

IPC: H01L2100

CPC classification number: H01L29/4908 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/78648 ,  H01L29/78654

Abstract: A method of fabricating a transistor using silicon on lattice matched insulator. A first monocrystalline silicon layer is provided and a first layer of dielectric is epitaxially deposited over the first silicon layer substantially lattice matched with the first silicon layer and substantially monocrystalline. A first electrically conductive gate electrode is epitaxially formed over the first layer of dielectric substantially lattice matched with the first layer of dielectric. A second layer of dielectric is epitaxially deposited conformally over the first gate electrode and exposed portions of first layer of dielectric substantially lattice matched with the first silicon layer and substantially monocrystalline. A second monocrystalline silicon layer is epitaxially deposited over the second layer of dielectric and a third layer of dielectric is epitaxially deposited over the second silicon layer substantially lattice matched with the first silicon layer and substantially monocrystalline. A second electrically conductive gate electrode is epitaxially deposited and formed over the third layer of dielectric which is substantially lattice matched with the first silicon layer and the first layer of dielectric. Source and drain regions are formed in the second silicon layer.

Abstract translation: 在晶格匹配绝缘体上制造使用硅的晶体管的方法。 提供第一单晶硅层，并且第一层电介质外延沉积在基本上与第一硅层晶格匹配并且基本上单晶的第一硅层上。 第一导电栅极电极外延形成在基本上与第一电介质层晶格匹配的电介质的第一层上。 电介质的第二层被外延地平铺地沉积在第一栅极电极上，并且第一介电层的暴露部分基本上与第一硅层晶格匹配并且基本上是单晶的。 第二单晶硅层外延沉积在第二层电介质上，并且第三层电介质外延沉积在第二硅层上，基本上与第一硅层基本上晶格匹配并且基本上是单晶。 第二导电栅电极被外延沉积并形成在与第一硅层和第一介电层基本上晶格匹配的第三电介质层上。 源极和漏极区域形成在第二硅层中。

公开(公告)号：US06528386B1

公开(公告)日：2003-03-04

申请号：US10097919

申请日：2002-03-13

Applicant: Scott R. Summerfelt ,  Luigi Colombo ,  Stephen R. Gilbert ,  Theodore S. Moise, IV ,  Sanjeev Aggarwal

Inventor： Scott R. Summerfelt ,  Luigi Colombo ,  Stephen R. Gilbert ,  Theodore S. Moise, IV ,  Sanjeev Aggarwal

IPC: H01L2176

CPC classification number: H01L27/11502 ,  H01L27/11507

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.

Abstract translation: 公开了一种制造铁电电容器的方法。 该方法包括图案化顶部电极层和电介质层以形成具有与其相关联的侧壁的电容器堆叠结构。 在图形化底部电极层之前，在电容器堆叠结构的侧壁上形成保护膜，以保护电介质材料免受与随后的底部电极层的图案化有关的导电污染物的影响。

公开(公告)号：US06362499B1

公开(公告)日：2002-03-26

申请号：US09645158

申请日：2000-08-24

Applicant: Theodore S. Moise ,  Scott R. Summerfelt

Inventor： Theodore S. Moise ,  Scott R. Summerfelt

IPC: H01L2976

CPC classification number: G11C29/44 ,  G11C11/223 ,  G11C2029/1208 ,  H01L21/28291 ,  H01L29/78391

Abstract: A ferroelectric structure on an integrated circuit and methods of making and using the same are disclosed, which may be used, for instance, in a high-speed, non-volatile, non-destructive readout random-access memory device. Generally, the ferroelectric structure combines a thin film ferroelectric variable resistor and a substrate (e.g. silicon) transistor, using a semiconducting film which is common to both. A field effect transistor 26 integrated into substrate 30 has a gate oxide 36 and a semiconducting gate electrode 38 with electrical connections at a first end 44 and a second end 46. Overlying gate electrode 38 is a ferroelectric thin film 40 and a conductive electrode 42. The polarization of ferroelectric thin film 40 is set by applying an appropriate voltage between gate electrode 38 and conductive electrode 42. The polarization of ferroelectric thin film 40 may be subsequently determined by applying a read voltage to 42 and 44, thus causing a voltage V2 to appear at 46 which is determined by the polarization of the ferroelectric variable resistor formed by 38 and 40. Since 38 also forms the gate electrode for field effect transistor 26, the magnitude of V2 affects the magnitude of current I2. Thus I2 is effectively an amplified signal related to the ferroelectric variable resistance which may be read without perturbing the polarization of ferroelectric thin film 40.

Abstract translation: 公开了集成电路中的铁电结构及其制造和使用的方法，其可以用于例如高速，非易失性，非破坏性读出随机存取存储器件中。 通常，铁电结构使用两者共同的半导体膜组合薄膜铁电可变电阻器和衬底（例如硅）晶体管。 集成到基板30中的场效应晶体管26具有在第一端44和第二端46具有电连接的栅极氧化物36和半导体栅电极38.叠层栅电极38是铁电薄膜40和导电电极42。 通过在栅电极38和导电电极42之间施加适当的电压来设定铁电薄膜40的极化。随后可以通过将读电压施加到42和44来确定铁电薄膜40的极化，从而使电压V2 出现在46处，其由38和40形成的铁电可变电阻器的极化决定。由于38还形成场效应晶体管26的栅电极，因此V2的大小影响电流I2的大小。 因此，I2实际上是与铁电可变电阻相关的放大信号，其可以在不扰乱铁电薄膜40的极化的情况下读取。

公开(公告)号：US06225655B1

公开(公告)日：2001-05-01

申请号：US08953947

申请日：1997-10-20

Applicant: Theodore S. Moise ,  Scott R. Summerfelt

Inventor： Theodore S. Moise ,  Scott R. Summerfelt

IPC: H01L2976

CPC classification number: G11C29/44 ,  G11C11/223 ,  G11C2029/1208 ,  H01L21/28291 ,  H01L29/78391

Abstract: A ferroelectric structure on an integrated circuit is disclosed, which may be used, for instance, in a high-speed, non-volatile, non-destructive readout random-access memory device. Generally, the ferroelectric structure combines a thin film ferroelectric variable resistor and a substrate (e.g. silicon) transistor, using a semiconducting film which is common to both. A field effect transistor 26 integrated into substrate 30 has a gate oxide 36 and a semiconducting gate electrode 38 with electrical connections at a first end 44 and a second end 46. Overlying gate electrode 38 is a ferroelectric thin film 40 and a conductive electrode 42. The polarization of ferroelectric thin film 40 is set by applying an appropriate voltage between gate electrode 38 and conductive electrode 42. The polarization of ferroelectric thin film 40 may be subsequently determined by applying a read voltage to 42 and 44, thus causing a voltage V2 to appear at 46 which is determined by the polarization of the ferroelectric variable resistor formed by 38 and 40. Since 38 also forms the gate electrode for field effect transistor 26, the magnitude of V2 affects the magnitude of current I2. Thus I2 is effectively an amplified signal related to the ferroelectric variable resistance which may be read without perturbing the polarization of ferroelectric thin film 40.

Abstract translation: 公开了集成电路中的铁电结构，其可以用于例如高速，非易失性，非破坏性读出随机存取存储器件中。 通常，铁电结构使用两者共同的半导体膜组合薄膜铁电可变电阻器和衬底（例如硅）晶体管。 集成到基板30中的场效应晶体管26具有在第一端44和第二端46具有电连接的栅极氧化物36和半导体栅电极38.叠层栅电极38是铁电薄膜40和导电电极42。 通过在栅电极38和导电电极42之间施加适当的电压来设定铁电薄膜40的极化。随后可以通过将读电压施加到42和44来确定铁电薄膜40的极化，从而使电压V2 出现在46处，其由38和40形成的铁电可变电阻器的极化决定。由于38还形成场效应晶体管26的栅电极，因此V2的大小影响电流I2的大小。 因此，I2实际上是与铁电可变电阻相关的放大信号，其可以在不扰乱铁电薄膜40的极化的情况下读取。

公开(公告)号：US06171970B2

公开(公告)日：2001-01-09

申请号：US09238211

申请日：1999-01-27

Applicant: Guoqiang Xing ,  Abbas Ali ,  Theodore S. Moise

Inventor： Guoqiang Xing ,  Abbas Ali ,  Theodore S. Moise

IPC: H01L213065

CPC classification number: H01L28/55 ,  H01L21/0332 ,  H01L21/32 ,  H01L21/32139 ,  H01L27/10814

Abstract: A method for etching a platinum surface 200. The method includes the step of forming a hardmask 202 including titanium, aluminum, and nitrogen on the platinum surface. The hardmask covers portions of the platinum surface. The method further includes removing platinum from uncovered portions of the surface with a plasma including a nitrogen-bearing species. The etch chemistry may also comprise an oxygen-bearing species.

Abstract translation: 一种用于蚀刻铂表面200的方法。该方法包括在铂表面上形成包括钛，铝和氮的硬掩模202的步骤。 硬掩模覆盖铂表面的部分。 该方法还包括用包括含氮物质的等离子体从表面的未覆盖部分去除铂。 蚀刻化学物质也可以包含含氧物质。

公开(公告)号：US20090233382A1

公开(公告)日：2009-09-17

申请号：US12472265

申请日：2009-05-26

Applicant: Theodore S. Moise, IV ,  Scott R. Summerfelt ,  K.R. Udayakumar

Inventor： Theodore S. Moise, IV ,  Scott R. Summerfelt ,  K.R. Udayakumar

IPC: H01L21/00

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55

Abstract: One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.

Abstract translation: 本发明的一个方面涉及一种制造集成电路的方法，包括在半导体衬底上形成铁电存储器单元的阵列，将衬底加热到​​铁电芯的居里温度附近的温度，并对衬底进行温度程序 ，由此当铁芯冷却至约室温时，铁电芯上的热诱导应力使芯的开关极化增加至少约25％。 本发明的实施例包括在铁电体芯上方和下方扩展横截面的金属填充通孔，其增加了在冷却期间铁电芯上的热应力。

公开(公告)号：US07183602B2

公开(公告)日：2007-02-27

申请号：US11033224

申请日：2005-01-11

Applicant: K. R. Udayakumar ,  Theodore S. Moise ,  Scott R. Summerfelt

Inventor： K. R. Udayakumar ,  Theodore S. Moise ,  Scott R. Summerfelt

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L27/11507 ,  H01L28/57

Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.

Abstract translation: 提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。 还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117） 氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。

公开(公告)号：US06686210B1

公开(公告)日：2004-02-03

申请号：US09349439

申请日：1999-07-09

Applicant: Stephen R. Gilbert ,  Theodore S. Moise ,  Scott R. Summerfelt

Inventor： Stephen R. Gilbert ,  Theodore S. Moise ,  Scott R. Summerfelt

IPC: H01L2100

CPC classification number: H01L28/55 ,  C23C16/40 ,  C23C16/409 ,  C23C16/44 ,  C23C16/517 ,  H01L21/31604 ,  H01L21/31691 ,  H01L27/0629 ,  H01L27/0805 ,  H01L28/60

Abstract: A method for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity by means of ion bombardment resulting in a texture with higher ferroelectric polarization or permittivity which is normally energetically disfavored.

Abstract translation: 通过离子轰击来控制具有各向异性铁电极化或介电常数的薄膜的晶体结构的方法，导致通常在能量上不利的铁电极化或介电常数较高的纹理。

公开(公告)号：US5905272A

公开(公告)日：1999-05-18

申请号：US960988

申请日：1997-10-30

Applicant: Theodore S. Moise

Inventor： Theodore S. Moise

IPC: H01L27/144 ,  H01L31/08 ,  H01L29/06

CPC classification number: B82Y10/00 ,  H01L27/144 ,  H01L31/08

Abstract: Apparatus for optical communications (10, 110, 210) includes a low-temperature grown photoconductor (12, 140, 220) coupled to at least one resonant tunneling device (14, 120, 130, 230, 240). When exposed to an input light, low-temperature grown photoconductor (10, 110, 210) absorbs photons, which decreases the resistivity, and thus the resistance of the photoconductor. This decrease in resistance causes a decrease in the voltage drop across photoconductor (12, 140, 220), which causes a corresponding increase in the voltage drop across resonant tunneling device (14, 120, 130, 230, 140).

Abstract translation: 用于光通信的装置（10,110,210）包括耦合到至少一个谐振隧穿装置（14,120,130,230,240）的低温生长的光电导体（12,140,​​220）。 当暴露于输入光时，低温生长的光电导体（10,110,210）吸收光子，这降低了电阻率，并因此降低了光电导体的电阻。 电阻的这种降低导致光电导体（12,140,​​220）上的电压降的降低，这导致谐振隧穿装置（14,120,130,230,140）上的电压降的相应增加。

公开(公告)号：US5442194A

公开(公告)日：1995-08-15

申请号：US178676

申请日：1994-01-07

Applicant: Theodore S. Moise

Inventor： Theodore S. Moise

IPC: H01L29/68 ,  H01L29/06 ,  H01L29/205 ,  H01L29/76 ,  H01L29/161 ,  H01L27/12 ,  H01L29/72

CPC classification number: H01L29/7606

Abstract: A hot-electron transistor (10) is formed on substrate (12) having an outer surface. The present transistor includes subcollector layer (14) comprising Indium Gallium Arsenide formed outwardly from the outer surface of substrate (12). Collector barrier layer (18) comprising Indium Aluminum Gallium Arsenide is outwardly formed from subcollector layer (14), and collector barrier layer (18) minimizes leakage current in transistor (10). Outwardly from collector barrier layer (18) is formed base layer (20) comprising Indium Gallium Arsenide. Tunnel injector layer (21) comprising Aluminum Arsenide for ballistically transporting electrons in transistor (10) is outwardly formed from base layer (20), and emitter layer (24) comprising Indium Aluminum Arsenide is outwardly formed from tunnel injector layer (21).

Abstract translation: 在具有外表面的基板（12）上形成热电子晶体管（10）。 本晶体管包括从基板（12）的外表面向外形成的包含砷化铟镓的子集电极层（14）。 包含铟铝镓砷化物的集电极阻挡层（18）由子集电极层（14）向外形成，并且集电极势垒层（18）使晶体管（10）中的漏电流最小化。 从集电极阻挡层（18）向外形成包含砷化镓的基底层（20）。 包括用于在晶体管（10）中弹性传输电子的砷化铝的隧道喷射器层（21）由基底层（20）向外形成，并且包括砷化铝铝的发射极层（24）由隧道喷射器层（21）向外形成。