公开(公告)号：US08290750B1

公开(公告)日：2012-10-16

申请号：US13036437

申请日：2011-02-28

申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

IPC分类号： H03F1/26

CPC分类号： H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

摘要翻译： 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

公开(公告)号：US20120057627A1

公开(公告)日：2012-03-08

申请号：US12875703

申请日：2010-09-03

申请人： Doris Po Ching Chan ,  Thungoc M. Tran

发明人： Doris Po Ching Chan ,  Thungoc M. Tran

IPC分类号： H03K5/159

CPC分类号： H04L25/03057 ,  H04L25/03885 ,  H04L2025/0349 ,  H04L2025/03636

摘要： Decision feedback equalizer (“DFE”) circuitry bases determination of the coefficients that are used in its various taps on the algebraic sign of the current value of an error signal and prior serial data signal values output by the DFE circuitry. Use of such algebraic sign information (rather than full error signal values) greatly simplifies the circuitry needed to determine the tap coefficients. The DFE circuitry can be adaptive, i.e., such that it automatically adjusts the tap coefficients for changing serial data signal transmission conditions.

摘要翻译： 判决反馈均衡器（“DFE”）电路基于在其各种抽头上使用的系数的确定，该误差信号的当前值的代数符号和DFE电路输出的先前串行数据信号值。 使用这种代数符号信息（而不是全错误信号值）大大简化了确定抽头系数所需的电路。 DFE电路可以是自适应的，即，其自动调整抽头系数以改变串行数据信号传输条件。

公开(公告)号：US07860203B1

公开(公告)日：2010-12-28

申请号：US11725653

申请日：2007-03-19

申请人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

发明人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H04J3/0688 ,  H04L7/033

摘要： A programmable logic device integrated circuit (“PLD”) includes high-speed serial interface (“HSSI”) circuitry in addition to programmable logic circuitry. The HSSI circuitry includes multiple channels of nominal data-handling circuitry (typically including clock and data recovery (“CDR”) circuitry), and at least one channel of nominal clock management unit (“CMU”) circuitry (typically including phase-locked loop (“PLL”) circuitry or the like). To increase the flexibility with which the channels can be used, the nominal data-handling channels are equipped to alternatively perform CMU-type functions, and the nominal CMU channel is equipped to alternatively perform data-handling functions.

摘要翻译： 可编程逻辑器件集成电路（“PLD”）除了可编程逻辑电路之外还包括高速串行接口（“HSSI”）电路。 HSSI电路包括多个标称数据处理电路（通常包括时钟和数据恢复（“CDR”）电路）的通道，以及标称时钟管理单元（“CMU”）电路的至少一个通道（通常包括锁相环 （“PLL”）电路等）。 为了增加可以使用信道的灵活性，标称数据处理信道被配备为交替执行CMU类型功能，并且标称CMU信道被配备为备选地执行数据处理功能。

公开(公告)号：US07855576B1

公开(公告)日：2010-12-21

申请号：US11407444

申请日：2006-04-19

申请人： Mei Luo ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Simardeep Maangat

发明人： Mei Luo ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Simardeep Maangat

IPC分类号： H03K19/0175 ,  H03K19/003

CPC分类号： H03K19/017509 ,  H04L25/0276

摘要： Methods and apparatus are provided for selectively setting a CM voltage for a transceiver, reducing the effect of current mismatch, and generating a voltage step that can be used for receiver detection. A circuit of the invention can include voltage generator circuitry operable to generate a plurality of voltage signals of substantially different voltages. The circuit can also include multiplexer circuitry with voltage inputs coupled to the voltage signals. The multiplexer circuitry can be operable to select a reference signal from among the voltage inputs. In addition, the circuit can include operational amplifier (“op-amp”) circuitry with a first input coupled to the reference signal and a second input coupled to an output signal of the op-amp circuitry.

摘要翻译： 提供了用于选择性地设置收发器的CM电压的方法和装置，减少电流失配的影响，以及产生可用于接收机检测的电压步骤。 本发明的电路可以包括可操作以产生具有实质上不同电压的多个电压信号的电压发生器电路。 电路还可以包括具有耦合到电压信号的电压输入的多路复用器电路。 多路复用器电路可以用于从电压输入中选择参考信号。 此外，电路可以包括运算放大器（“运算放大器”）电路，其中耦合到参考信号的第一输入和耦合到运放电路的输出信号的第二输入。

公开(公告)号：US07777526B2

公开(公告)日：2010-08-17

申请号：US12134777

申请日：2008-06-06

申请人： Sergey Shumarayev ,  Thungoc M. Tran ,  Wilson Wong ,  Simardeep Maangat

发明人： Sergey Shumarayev ,  Thungoc M. Tran ,  Wilson Wong ,  Simardeep Maangat

IPC分类号： H03K19/094

CPC分类号： H03K19/018514 ,  H03F3/45197 ,  H03F2203/45494 ,  H03F2203/45686

摘要： Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuit elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.

摘要翻译： 集成电路中晶体管变化/失配引起的信号偏移变化可能会降低。 在一个实施例中，缓冲电路具有可变值电路元件。 进行偏移变化测量，并校准可变值电路元件以减少测量的偏移变化。 在另一个实施例中，多级缓冲器的每个放大级提供可变增益。 级联的总直流增益不均匀地分布在整个级中，在级联开始时比放大器级提供更多的直流增益。 在级联开始时也可以提供一个额外的前级放大器级。

公开(公告)号：US20090011716A1

公开(公告)日：2009-01-08

申请号：US11773234

申请日：2007-07-03

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H04Q7/20

CPC分类号： H04L25/45

摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

摘要翻译： 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

公开(公告)号：US07460040B1

公开(公告)日：2008-12-02

申请号：US11754670

申请日：2007-05-29

申请人： Thungoc M. Tran ,  Yu Xu ,  Kwong-Wen Wei ,  Sergey Shumarayev

发明人： Thungoc M. Tran ,  Yu Xu ,  Kwong-Wen Wei ,  Sergey Shumarayev

IPC分类号： H03M9/00

CPC分类号： H03M9/00 ,  H03K5/135 ,  H03K19/1774 ,  H03K19/17744

摘要： A high-speed serial interface for a programmable logic device includes a plurality of features to handle the various issues that may arise with data rates over 1 Gbps and particularly over 1.25 Gbps. Those features may include dynamic phase alignment to control clock-data skew, data realignment (e.g., bit slip circuitry) to account for channel-to-channel skew, full-duplex serializer and deserializer, out-of-range frequency support for low frequencies, and a soft-CDR mode.

摘要翻译： 用于可编程逻辑器件的高速串行接口包括多个特征，以处理在1Gbps，特别是超过1.25Gbps的数据速率下可能出现的各种问题。 这些特征可以包括动态相位对准以控制时钟数据偏移，数据重新对准（例如位移电路）以解决通道间通道偏移，全双工串行器和解串器，超低频率频率支持 ，和软CDR模式。

公开(公告)号：US08571059B1

公开(公告)日：2013-10-29

申请号：US13194536

申请日：2011-07-29

申请人： Arch Zaliznyak ,  Ramanand Venkata ,  Surinder Singh ,  Henry Y. Lui ,  Tim Tri Hoang ,  Sergey Shumarayev ,  Thungoc M. Tran

发明人： Arch Zaliznyak ,  Ramanand Venkata ,  Surinder Singh ,  Henry Y. Lui ,  Tim Tri Hoang ,  Sergey Shumarayev ,  Thungoc M. Tran

IPC分类号： H04J3/00

CPC分类号： G06F13/385

摘要： Disclosed are apparatus and methods for providing a serial interface with shared datapaths. The apparatus and methods share or re-use components from multiple lower-speed datapaths so as to efficiently provide a higher-speed datapath. In one embodiment, physical coding sublayer circuitry of the lower-speed datapaths is also used by the higher-speed datapath. In another embodiment, physical media access circuitry of the lower-speed data paths is also used by the higher-speed datapath. Other embodiments, aspects and features are also disclosed.

摘要翻译： 公开了用于提供具有共享数据路径的串行接口的装置和方法。 该装置和方法共享或重新使用来自多个低速数据路径的组件，以便有效地提供更高速度的数据通路。 在一个实施例中，低速数据路径的物理编码子层电路也被较高速数据路径使用。 在另一个实施例中，低速数据路径的物理介质访问电路也被高速数据路径使用。 还公开了其它实施例，方面和特征。

公开(公告)号：US08417752B1

公开(公告)日：2013-04-09

申请号：US12470254

申请日：2009-05-21

申请人： Doris Po Ching Chan ,  Simardeep Maangat ,  Thungoc M. Tran ,  Sergey Shumarayev

发明人： Doris Po Ching Chan ,  Simardeep Maangat ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC分类号： G06F7/10 ,  G06F7/00

CPC分类号： H04B3/04

摘要： An equalizer circuitry that includes an equalizer stage having a programmable current source is described. In one implementation, the programmable current source cancels voltage offset. Also, in one implementation, the programmable current source is programmable in user mode. Furthermore, in one implementation, the equalizer circuitry includes a plurality of equalizer stages including the equalizer stage having a programmable current source, where the equalizer stage having a programmable current source is a second equalizer stage in the plurality of equalizer stages. Also, in one implementation, the programmable current source includes a plurality of current sources coupled in parallel and a plurality of sets of control switches for controlling the plurality of current sources. Further, in one implementation, each current source of the plurality of current sources includes a transistor and each set of control switches of the plurality of sets of control switches is for controlling a respective current source and includes a pair of transistors for controlling the respective current source.

摘要翻译： 描述了包括具有可编程电流源的均衡器级的均衡器电路。 在一个实现中，可编程电流源消除电压偏移。 而且，在一个实现中，可编程电流源可在用户模式下编程。 此外，在一个实现中，均衡器电路包括多个均衡器级，包括具有可编程电流源的均衡器级，其中具有可编程电流源的均衡器级是多个均衡器级中的第二均衡器级。 而且，在一个实现中，可编程电流源包括并联耦合的多个电流源和用于控制多个电流源的多组控制开关。 此外，在一个实现中，多个电流源的每个电流源包括晶体管，并且多组控制开关中的每组控制开关用于控制相应的电流源，并且包括用于控制相应电流的一对晶体管 资源。

公开(公告)号：US08127215B2

公开(公告)日：2012-02-28

申请号：US13151717

申请日：2011-06-02

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H03M13/03

CPC分类号： H04L25/45

摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

摘要翻译： 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。