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    Apparatus and methods for serial interfaces with shared datapaths
    1.
    发明授权
    Apparatus and methods for serial interfaces with shared datapaths 有权
    具有共享数据路径的串行接口的装置和方法

    公开(公告)号：US08571059B1

    公开(公告)日：2013-10-29

    申请号：US13194536

    申请日：2011-07-29

    申请人： Arch Zaliznyak ,  Ramanand Venkata ,  Surinder Singh ,  Henry Y. Lui ,  Tim Tri Hoang ,  Sergey Shumarayev ,  Thungoc M. Tran

    发明人： Arch Zaliznyak ,  Ramanand Venkata ,  Surinder Singh ,  Henry Y. Lui ,  Tim Tri Hoang ,  Sergey Shumarayev ,  Thungoc M. Tran

    IPC分类号： H04J3/00

    CPC分类号： G06F13/385

    摘要： Disclosed are apparatus and methods for providing a serial interface with shared datapaths. The apparatus and methods share or re-use components from multiple lower-speed datapaths so as to efficiently provide a higher-speed datapath. In one embodiment, physical coding sublayer circuitry of the lower-speed datapaths is also used by the higher-speed datapath. In another embodiment, physical media access circuitry of the lower-speed data paths is also used by the higher-speed datapath. Other embodiments, aspects and features are also disclosed.

    摘要翻译： 公开了用于提供具有共享数据路径的串行接口的装置和方法。 该装置和方法共享或重新使用来自多个低速数据路径的组件，以便有效地提供更高速度的数据通路。 在一个实施例中，低速数据路径的物理编码子层电路也被较高速数据路径使用。 在另一个实施例中，低速数据路径的物理介质访问电路也被高速数据路径使用。 还公开了其它实施例，方面和特征。

    Techniques for providing clock signals in clock networks
    3.
    发明授权
    Techniques for providing clock signals in clock networks 有权
    在时钟网络中提供时钟信号的技术

    公开(公告)号：US08581653B1

    公开(公告)日：2013-11-12

    申请号：US13328784

    申请日：2011-12-16

    申请人： Victor Maruri ,  Arch Zaliznyak ,  Ramanand Venkata ,  Henry Y. Lui

    发明人： Victor Maruri ,  Arch Zaliznyak ,  Ramanand Venkata ,  Henry Y. Lui

    IPC分类号： G06F1/04 ,  H03K3/00

    CPC分类号： G06F1/10

    摘要： An integrated circuit includes a local clock network that is operable to provide a first clock signal and an interface circuit that is coupled to receive the first clock signal from the local clock network. The interface circuit is operable to generate a second clock signal based on the first clock signal. A clock line is coupled to the interface circuit. The clock line has a fixed length. The second clock signal is provided to a multiplexer circuit through the clock line. The multiplexer circuit provides a third clock signal based on the second clock signal. Another clock network is coupled to receive the third clock signal from the multiplexer circuit.

    摘要翻译： 集成电路包括可操作以提供第一时钟信号的本地时钟网络和耦合以从本地时钟网络接收第一时钟信号的接口电路。 接口电路可操作以基于第一时钟信号产生第二时钟信号。 时钟线耦合到接口电路。 时钟线具有固定长度。 第二时钟信号通过时钟线提供给多路复用器电路。 多路复用器电路基于第二时钟信号提供第三时钟信号。 另一个时钟网络被耦合以从多路复用器电路接收第三时钟信号。

    Multi-channel communication circuitry for programmable logic device integrated circuits and the like
    6.
    发明授权
    Multi-channel communication circuitry for programmable logic device integrated circuits and the like 有权
    用于可编程逻辑器件集成电路等的多通道通信电路

    公开(公告)号：US07656187B2

    公开(公告)日：2010-02-02

    申请号：US11288810

    申请日：2005-11-28

    申请人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

    发明人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/17744

    摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.

    摘要翻译： 诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。 提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作 一起，八个渠道在一起等）。 共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。 电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以便于诸如电路设计和验证之类的事情。

    Techniques for Aligning and Reducing Skew in Serial Data Signals
    7.
    发明申请
    Techniques for Aligning and Reducing Skew in Serial Data Signals 有权
    在串行数据信号中对齐和减少偏移的技术

    公开(公告)号：US20140035642A1

    公开(公告)日：2014-02-06

    申请号：US13566882

    申请日：2012-08-03

    申请人： Ramanand Venkata ,  Henry Lui ,  Arch Zaliznyak

    发明人： Ramanand Venkata ,  Henry Lui ,  Arch Zaliznyak

    IPC分类号： H03K5/1534

    CPC分类号： H03K5/1534

    摘要： A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.

    摘要翻译： 一个电路包括第一和第二对准器电路和一个去歪斜电路。 第一对准器电路可操作以将第一输入串行数据信号与控制信号对准以产生第一对准的串行数据信号。 第二对准器电路可操作以将第二输入串行数据信号与控制信号对准以产生第二对准的串行数据信号。 去偏置电路可操作以减少第一和第二对准的串行数据信号之间的偏差，以产生第一和第二输出串行数据信号。

    Techniques for aligning and reducing skew in serial data signals
    8.
    发明授权
    Techniques for aligning and reducing skew in serial data signals 有权
    用于对齐和减少串行数据信号偏移的技术

    公开(公告)号：US08994425B2

    公开(公告)日：2015-03-31

    申请号：US13566882

    申请日：2012-08-03

    申请人： Ramanand Venkata ,  Henry Lui ,  Arch Zaliznyak

    发明人： Ramanand Venkata ,  Henry Lui ,  Arch Zaliznyak

    IPC分类号： H03L7/00 ,  H03K5/1534

    CPC分类号： H03K5/1534

    摘要： A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.

    摘要翻译： 一个电路包括第一和第二对准器电路和一个去歪斜电路。 第一对准器电路可操作以将第一输入串行数据信号与控制信号对准以产生第一对准的串行数据信号。 第二对准器电路可操作以将第二输入串行数据信号与控制信号对准以产生第二对准的串行数据信号。 去偏置电路可操作以减少第一和第二对准的串行数据信号之间的偏差，以产生第一和第二输出串行数据信号。