公开(公告)号：US20070120151A1

公开(公告)日：2007-05-31

申请号：US11668477

申请日：2007-01-30

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L29/76

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

Abstract: A NVM including a substrate, a control gate layer, a charge storage layer, a tunneling layer, a charge barrier layer, a gate dielectric layer and a first doping region is described. The control gate layer is disposed in a first trench of the substrate; the charge storage layer is disposed between the sidewall of the first trench and the control gate layer; the tunneling layer is disposed between the sidewall of the first trench and the charge storage layer; the charge barrier layer is disposed between the charge storage layer and the control gate layer; the gate dielectric layer is disposed between the bottom of the first trench and the control gate layer; and the first doping region is disposed in the substrate at one side of the control gate layer.

Abstract translation: 描述了包括基板，控制栅极层，电荷存储层，隧道层，电荷势垒层，栅极介电层和第一掺杂区域的NVM。 控制栅极层设置在衬底的第一沟槽中; 电荷存储层设置在第一沟槽的侧壁和控制栅极层之间; 隧道层设置在第一沟槽的侧壁和电荷存储层之间; 电荷阻挡层设置在电荷存储层和控制栅极层之间; 栅介电层设置在第一沟槽的底部和控制栅极层之间; 并且第一掺杂区域设置在控制栅极层的一侧的衬底中。

公开(公告)号：US20060275976A1

公开(公告)日：2006-12-07

申请号：US11161724

申请日：2005-08-15

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/76

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

Abstract: A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a tunneling layer and a charge storage layer are sequentially formed on both sidewalls of each second trench. An isolation layer is filled into the first trench. Furthermore, a charge barrier layer is formed on the sidewall of the second trench, and a gate dielectric layer is formed at the bottom of the second trench. A control gate layer is filled into the second trench. Finally, two first doping regions are formed in the substrate at both sides of the control gate layer.

Abstract translation: 提供了一种用于非易失性存储器的制造方法。 为了制造非易失性存储器，在衬底中形成多个第一沟槽和第二沟槽，其中第二沟槽设置在第一沟槽上方并跨过第一沟槽。 然后，在每个第二沟槽的两个侧壁上依次形成隧穿层和电荷存储层。 隔离层被填充到第一沟槽中。 此外，在第二沟槽的侧壁上形成电荷阻挡层，在第二沟槽的底部形成栅极电介质层。 控制栅极层被填充到第二沟槽中。 最后，在控制栅极层两侧的衬底中形成两个第一掺杂区。

公开(公告)号：US20060057848A1

公开(公告)日：2006-03-16

申请号：US10979161

申请日：2004-11-03

Applicant: Meng Cheng ,  Ya Ling Po ,  Ting Sing Wang

Inventor： Meng Cheng ,  Ya Ling Po ,  Ting Sing Wang

IPC: H01L21/302

CPC classification number: H01L29/66181 ,  H01L21/30604 ,  H01L21/30608 ,  H01L27/1087

Abstract: The method for preparing a deep trench uses a dry etching process to form a trench in a silicon substrate, and an etching mixture is then coated on the surface of the silicon substrate and inside the deep trench. A portion of etching mixture is removed from the surface of the silicon substrate and the trench above a predetermined depth from the surface of the substrate, and an etching process is then performed using the etching mixture remaining inside the trench to etch the silicon substrate below the predetermined depth so as to form the deep trench. The etching mixture comprises a conveying solution and an etchant, and the viscosity of the conveying solution is higher than that of the etchant. The conveying solution is spin-on-glass or a photoresist, and the etchant is tetramethylammonium hydroxide, ammonium, or hydrofluoric acid. The volume ratio of the conveying solution and the etchant is preferably between 50:1 and 20:1.

公开(公告)号：US06180980B2

公开(公告)日：2001-01-30

申请号：US09376464

申请日：1999-08-18

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L2178

CPC classification number: H01L29/66825 ,  H01L21/28273

Abstract: A method of manufacturing a trench non-volatile memory cell, comprises the steps of: providing a semiconductor substrate; performing ion implantation to form a source region in the semiconductor substrate; forming a trench on the semiconductor substrate by silicon etching, the trench reaching down to the source region; growing a first isolation layer on the surface of the semiconductor substrate, and the bottom and sidewall of the trench; forming a hollow-shaped first conducting layer in the trench; performing thermal oxidation on the first conducting layer to form a bird's beak isolation layer and a floating gate, which are the oxidized and unoxidized part of the first conducting layer, respectively, wherein the floating gate has a peak; partially removing the first isolation layer and the bird's beak isolation layer to bare the surface of the semiconductor substrate, the peak and the sidewall of the trench; depositing a second conducting layer; patterning the second conducting layer to form a control gate; and defining a drain region in the semiconductor substrate.

Abstract translation: 一种制造沟槽非易失性存储单元的方法，包括以下步骤：提供半导体衬底; 执行离子注入以在半导体衬底中形成源极区; 通过硅蚀刻在半导体衬底上形成沟槽，沟槽到达源区; 在半导体衬底的表面上以及沟槽的底部和侧壁上生长第一隔离层; 在沟槽中形成中空状的第一导电层; 在所述第一导电层上进行热氧化以形成分别为所述第一导电层的氧化和未氧化部分的鸟喙隔离层和浮栅，其中所述浮栅具有峰; 部分地去除第一隔离层和鸟嘴隔离层以露出半导体衬底的表面，沟槽的峰和侧壁; 沉积第二导电层; 图案化第二导电层以形成控制栅极; 以及限定半导体衬底中的漏区。

公开(公告)号：US20090014787A1

公开(公告)日：2009-01-15

申请号：US11969702

申请日：2008-01-04

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7811 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4941 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: A power MOSFET structure comprises at least one first gate in the cell area and at least one second gate at the peripheral that are both in a semiconductor substrate. The first and second gates are electrically connected, and the second gate is connected to a contact so as to electrically connect to a bond pad for transmitting gate control signals. The semiconductor substrate comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in downward sequence. The first and third semiconductor layers are of a first conductive type, e.g., n-type, and the second semiconductor layer is of a second conductive type, e.g., p-type. The first and third semiconductor layers serve as the source and the drain, respectively.

Abstract translation: 功率MOSFET结构包括在单元区域中的至少一个第一栅极和位于半导体衬底中的至少一个外围的第二栅极。 第一和第二栅极电连接，并且第二栅极连接到触点，以便电连接到用于传输栅极控制信号的接合焊盘。 半导体衬底包括第一半导体层，第二半导体层和第三半导体层。 第一和第三半导体层是第一导电类型，例如n型，并且第二半导体层是第二导电类型，例如p型。 第一和第三半导体层分别用作源极和漏极。

公开(公告)号：US20070158719A1

公开(公告)日：2007-07-12

申请号：US11402871

申请日：2006-04-13

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L29/94

CPC classification number: H01L29/7841 ,  H01L27/108 ,  H01L27/10802

Abstract: A dynamic random access memory structure having a vertical floating body cell includes a semiconductor substrate having a plurality of cylindrical pillars, an upper conductive region positioned on a top portion of the cylindrical pillar, a body positioned below the upper conductive portion in the cylindrical pillar, a bottom conductive portion positioned below the body in the cylindrical pillar, a gate oxide layer surrounding the sidewall of the cylindrical pillar and a gate structure surrounding the gate oxide layer. The upper conductive region serves as a drain electrode, the bottom conductive region serves as a source electrode and the body can store carriers such as holes. Preferably, the dynamic random access memory structure further comprises a conductive layer positioned on the surface of the semiconductor substrate to electrically connect the bottom conductive regions in the cylindrical pillars.

Abstract translation: 具有垂直浮体单元的动态随机存取存储器结构包括具有多个圆柱形柱状物的半导体衬底，位于圆柱形柱体顶部的上部导电区域，位于圆柱形柱体中的上部导电部分下方的主体， 位于圆柱形柱体的主体下方的底部导电部分，围绕圆柱形柱的侧壁的栅极氧化物层和围绕栅极氧化物层的栅极结构。 上导电区域用作漏电极，底部导电区域用作源电极，并且主体可以存储诸如孔的载体。 优选地，动态随机存取存储器结构还包括位于半导体衬底的表面上的导电层，以电连接圆柱形支柱中的底部导电区域。

公开(公告)号：US07094697B2

公开(公告)日：2006-08-22

申请号：US10979161

申请日：2004-11-03

Applicant: Meng Fen Cheng ,  Ya Ling Po ,  Ting Sing Wang

Inventor： Meng Fen Cheng ,  Ya Ling Po ,  Ting Sing Wang

IPC: H01L21/311 ,  H01L21/8242 ,  H01L21/20

CPC classification number: H01L29/66181 ,  H01L21/30604 ,  H01L21/30608 ,  H01L27/1087

Abstract: The method for preparing a deep trench uses a dry etching process to form a trench in a silicon substrate, and an etching mixture is then coated on the surface of the silicon substrate and inside the deep trench. A portion of etching mixture is removed from the surface of the silicon substrate and the trench above a predetermined depth from the surface of the substrate, and an etching process is then performed using the etching mixture remaining inside the trench to etch the silicon substrate below the predetermined depth so as to form the deep trench. The etching mixture comprises a conveying solution and an etchant, and the viscosity of the conveying solution is higher than that of the etchant. The conveying solution is spin-on-glass or a photoresist, and the etchant is tetramethylammonium hydroxide, ammonium, or hydrofluoric acid. The volume ratio of the conveying solution and the etchant is preferably between 50:1 and 20:1.

Abstract translation: 制备深沟槽的方法使用干蚀刻工艺在硅衬底中形成沟槽，然后将蚀刻混合物涂覆在硅衬底的表面上和深沟槽内。 蚀刻混合物的一部分从硅衬底的表面和沟槽上方超过衬底表面的预定深度去除，然后使用残留在沟槽内的蚀刻混合物进行蚀刻工艺，以将硅衬底 预定深度以形成深沟槽。 蚀刻混合物包括输送溶液和蚀刻剂，并且输送溶液的粘度高于蚀刻剂的粘度。 输送溶液是旋涂玻璃或光致抗蚀剂，蚀刻剂是四甲基氢氧化铵，铵或氢氟酸。 输送溶液和蚀刻剂的体积比优选为50:1至20:1。

公开(公告)号：US4917467A

公开(公告)日：1990-04-17

申请号：US207753

申请日：1988-06-16

Applicant: Hsiung-Ku Chen ,  Ting-Sing Wang ,  Chia-Wei Hao

Inventor： Hsiung-Ku Chen ,  Ting-Sing Wang ,  Chia-Wei Hao

IPC: G02F1/133 ,  G02F1/1343 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/36 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L49/02

CPC classification number: H01L27/12 ,  G02F1/13624 ,  G02F1/136259

Abstract: A TFT LCD device is comprised of four TFT's with two separate sources, two separate drains and one common source-drain which is shared by the four respective TFT's, either acting as source or drain. The gate structure employs only one gate line with a bypass line. By sharing of the Si island and the centralization of the gate electrode of four TFT's, the pixel open ratio increases quite substantially. The devices are connected to the two adjacent pixels separated by the gate line via the two drain electrodes. Each pixel electrode is connected to the two adjacent devices via the two drain electrodes. Each pixel electrode can receive the data signals which are controlled by the two adjacent devices, to form a redundant structure for improving the yield of the TFT LCD. The common source-drain is situated along the gate bus line, and doesn't occupy too much of the pixel area, to thereby provide a large open ratio.

Abstract translation: TFT LCD器件由四个TFT组成，具有两个独立的源极，两个独立的漏极和一个共同的源极 - 漏极，由四个相应的TFT共享，作为源极或漏极。 栅极结构仅使用一条带旁路线的栅极线。 通过共享Si岛和四个TFT的栅电极的集中，像素开放比率显着增加。 这些器件通过两个漏电极连接到由栅极线分开的两个相邻像素。 每个像素电极经由两个漏电极连接到两个相邻的器件。 每个像素电极可以接收由两个相邻器件控制的数据信号，以形成用于提高TFT LCD的产量的冗余结构。 公共源极 - 漏极沿着栅极总线布置，并且不占用像素面积太多，从而提供大的开放比。