公开(公告)号：US07622352B2

公开(公告)日：2009-11-24

申请号：US11440075

申请日：2006-05-25

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L21/336

CPC classification number: H01L29/1037 ,  H01L21/28114 ,  H01L21/28141 ,  H01L29/1045 ,  H01L29/42376 ,  H01L29/66659

Abstract: A multi-step gate structure comprises a semiconductor substrate having a multi-step structure, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the gate oxide layer has different thicknesses on each step surface of the multi-step structure. In addition, the multi-step gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure. The channel length of the multi-step gate structure is the summation of the lateral width and the vertical depth of the multi-step gate structure, which is dramatically increased such that problems originated from the short channel effect can be effectively solved. Further, the plurality of doped regions under the multi-step structure are prepared by implanting processes having different dosages and dopants, which can control the thickness of the gate oxide layer and the threshold voltage of the multi-step gate structure.

Abstract translation: 多级栅极结构包括具有多级结构的半导体衬底，位于多级结构上的栅极氧化物层和位于栅极氧化物层上的导电层。 优选地，栅极氧化物层在多步骤结构的每个台阶表面上具有不同的厚度。 此外，多步栅极结构还包括在多步结构下定位在半导体衬底中的多个掺杂区域。 多级栅极结构的沟道长度是多级栅极结构的横向宽度和垂直深度的总和，其显着增加，从而可以有效地解决源自短沟道效应的问题。 此外，通过注入具有不同剂量和掺杂剂的工艺来制备多步结构下的多个掺杂区域，其可以控制栅极氧化物层的厚度和多步栅极结构的阈值电压。

公开(公告)号：US07557407B2

公开(公告)日：2009-07-07

申请号：US11435848

申请日：2006-05-18

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/42368 ,  H01L21/28141 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/7834

Abstract: A recessed gate structure comprises a semiconductor substrate, a recess positioned in the semiconductor substrate, a gate oxide layer positioned in the recess and a conductive layer positioned on the gate oxide layer, wherein the semiconductor substrate has a multi-step structure in the recess. The thickness of the gate oxide layer on one step surface can be different from that on another step surface of the multi-step structure. In addition, the recessed gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure, and these doped regions may use different dosages and different types of dopants. There is a carrier channel in the semiconductor substrate under the recessed gate structure and the overall channel length of the carrier channel is substantially the summation of the lateral width and twice of the vertical depth of the recessed gate structure.

Abstract translation: 凹陷栅极结构包括半导体衬底，位于半导体衬底中的凹部，位于凹槽中的栅极氧化物层和位于栅极氧化物层上的导电层，其中半导体衬底在凹部中具有多级结构。 一步表面上的栅极氧化层的厚度可以与多步结构的另一台阶表面上的厚度不同。 此外，凹陷栅极结构还包括在多步结构下定位在半导体衬底中的多个掺杂区域，并且这些掺杂区域可以使用不同的剂量和不同类型的掺杂剂。 在凹陷栅极结构下方的半导体衬底中存在载流子通道，并且载流子通道的整体沟道长度基本上是凹入栅极结构的横向宽度和垂直深度的两倍的总和。

公开(公告)号：US07456458B2

公开(公告)日：2008-11-25

申请号：US11402871

申请日：2006-04-13

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L27/108

CPC classification number: H01L29/7841 ,  H01L27/108 ,  H01L27/10802

Abstract: A dynamic random access memory structure having a vertical floating body cell includes a semiconductor substrate having a plurality of cylindrical pillars, an upper conductive region positioned on a top portion of the cylindrical pillar, a body positioned below the upper conductive portion in the cylindrical pillar, a bottom conductive portion positioned below the body in the cylindrical pillar, a gate oxide layer surrounding the sidewall of the cylindrical pillar and a gate structure surrounding the gate oxide layer. The upper conductive region serves as a drain electrode, the bottom conductive region serves as a source electrode and the body can store carriers such as holes. Preferably, the dynamic random access memory structure further comprises a conductive layer positioned on the surface of the semiconductor substrate to electrically connect the bottom conductive regions in the cylindrical pillars.

Abstract translation: 具有垂直浮体单元的动态随机存取存储器结构包括具有多个圆柱形柱状物的半导体衬底，位于圆柱形柱体顶部的上部导电区域，位于圆柱形柱体中的上部导电部分下方的主体， 位于圆柱形柱体的主体下方的底部导电部分，围绕圆柱形柱的侧壁的栅极氧化物层和围绕栅极氧化物层的栅极结构。 上导电区域用作漏电极，底部导电区域用作源电极，并且主体可以存储诸如孔的载体。 优选地，动态随机存取存储器结构还包括位于半导体衬底的表面上的导电层，以电连接圆柱形支柱中的底部导电区域。

公开(公告)号：US20060057848A1

公开(公告)日：2006-03-16

申请号：US10979161

申请日：2004-11-03

Applicant: Meng Cheng ,  Ya Ling Po ,  Ting Sing Wang

Inventor： Meng Cheng ,  Ya Ling Po ,  Ting Sing Wang

IPC: H01L21/302

CPC classification number: H01L29/66181 ,  H01L21/30604 ,  H01L21/30608 ,  H01L27/1087

Abstract: The method for preparing a deep trench uses a dry etching process to form a trench in a silicon substrate, and an etching mixture is then coated on the surface of the silicon substrate and inside the deep trench. A portion of etching mixture is removed from the surface of the silicon substrate and the trench above a predetermined depth from the surface of the substrate, and an etching process is then performed using the etching mixture remaining inside the trench to etch the silicon substrate below the predetermined depth so as to form the deep trench. The etching mixture comprises a conveying solution and an etchant, and the viscosity of the conveying solution is higher than that of the etchant. The conveying solution is spin-on-glass or a photoresist, and the etchant is tetramethylammonium hydroxide, ammonium, or hydrofluoric acid. The volume ratio of the conveying solution and the etchant is preferably between 50:1 and 20:1.

公开(公告)号：US20090014787A1

公开(公告)日：2009-01-15

申请号：US11969702

申请日：2008-01-04

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7811 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4941 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: A power MOSFET structure comprises at least one first gate in the cell area and at least one second gate at the peripheral that are both in a semiconductor substrate. The first and second gates are electrically connected, and the second gate is connected to a contact so as to electrically connect to a bond pad for transmitting gate control signals. The semiconductor substrate comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in downward sequence. The first and third semiconductor layers are of a first conductive type, e.g., n-type, and the second semiconductor layer is of a second conductive type, e.g., p-type. The first and third semiconductor layers serve as the source and the drain, respectively.

Abstract translation: 功率MOSFET结构包括在单元区域中的至少一个第一栅极和位于半导体衬底中的至少一个外围的第二栅极。 第一和第二栅极电连接，并且第二栅极连接到触点，以便电连接到用于传输栅极控制信号的接合焊盘。 半导体衬底包括第一半导体层，第二半导体层和第三半导体层。 第一和第三半导体层是第一导电类型，例如n型，并且第二半导体层是第二导电类型，例如p型。 第一和第三半导体层分别用作源极和漏极。

公开(公告)号：US20070158719A1

公开(公告)日：2007-07-12

申请号：US11402871

申请日：2006-04-13

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L29/94

CPC classification number: H01L29/7841 ,  H01L27/108 ,  H01L27/10802

Abstract: A dynamic random access memory structure having a vertical floating body cell includes a semiconductor substrate having a plurality of cylindrical pillars, an upper conductive region positioned on a top portion of the cylindrical pillar, a body positioned below the upper conductive portion in the cylindrical pillar, a bottom conductive portion positioned below the body in the cylindrical pillar, a gate oxide layer surrounding the sidewall of the cylindrical pillar and a gate structure surrounding the gate oxide layer. The upper conductive region serves as a drain electrode, the bottom conductive region serves as a source electrode and the body can store carriers such as holes. Preferably, the dynamic random access memory structure further comprises a conductive layer positioned on the surface of the semiconductor substrate to electrically connect the bottom conductive regions in the cylindrical pillars.

Abstract translation: 具有垂直浮体单元的动态随机存取存储器结构包括具有多个圆柱形柱状物的半导体衬底，位于圆柱形柱体顶部的上部导电区域，位于圆柱形柱体中的上部导电部分下方的主体， 位于圆柱形柱体的主体下方的底部导电部分，围绕圆柱形柱的侧壁的栅极氧化物层和围绕栅极氧化物层的栅极结构。 上导电区域用作漏电极，底部导电区域用作源电极，并且主体可以存储诸如孔的载体。 优选地，动态随机存取存储器结构还包括位于半导体衬底的表面上的导电层，以电连接圆柱形支柱中的底部导电区域。

公开(公告)号：US07094697B2

公开(公告)日：2006-08-22

申请号：US10979161

申请日：2004-11-03

Applicant: Meng Fen Cheng ,  Ya Ling Po ,  Ting Sing Wang

Inventor： Meng Fen Cheng ,  Ya Ling Po ,  Ting Sing Wang

IPC: H01L21/311 ,  H01L21/8242 ,  H01L21/20

CPC classification number: H01L29/66181 ,  H01L21/30604 ,  H01L21/30608 ,  H01L27/1087

Abstract: The method for preparing a deep trench uses a dry etching process to form a trench in a silicon substrate, and an etching mixture is then coated on the surface of the silicon substrate and inside the deep trench. A portion of etching mixture is removed from the surface of the silicon substrate and the trench above a predetermined depth from the surface of the substrate, and an etching process is then performed using the etching mixture remaining inside the trench to etch the silicon substrate below the predetermined depth so as to form the deep trench. The etching mixture comprises a conveying solution and an etchant, and the viscosity of the conveying solution is higher than that of the etchant. The conveying solution is spin-on-glass or a photoresist, and the etchant is tetramethylammonium hydroxide, ammonium, or hydrofluoric acid. The volume ratio of the conveying solution and the etchant is preferably between 50:1 and 20:1.

Abstract translation: 制备深沟槽的方法使用干蚀刻工艺在硅衬底中形成沟槽，然后将蚀刻混合物涂覆在硅衬底的表面上和深沟槽内。 蚀刻混合物的一部分从硅衬底的表面和沟槽上方超过衬底表面的预定深度去除，然后使用残留在沟槽内的蚀刻混合物进行蚀刻工艺，以将硅衬底 预定深度以形成深沟槽。 蚀刻混合物包括输送溶液和蚀刻剂，并且输送溶液的粘度高于蚀刻剂的粘度。 输送溶液是旋涂玻璃或光致抗蚀剂，蚀刻剂是四甲基氢氧化铵，铵或氢氟酸。 输送溶液和蚀刻剂的体积比优选为50:1至20:1。