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39 条记录 (耗时 0.017 秒)

    SEAL RING STRUCTURE FOR INTEGRATED CIRCUITS
    14.
    发明申请
    SEAL RING STRUCTURE FOR INTEGRATED CIRCUITS 审中-公开
    集成电路密封圈结构

    公开(公告)号：US20090294897A1

    公开(公告)日：2009-12-03

    申请号：US12340737

    申请日：2008-12-21

    申请人： Tung-Hsing Lee ,  Tien-Chang Chang ,  Yuan-Hung Chung

    发明人： Tung-Hsing Lee ,  Tien-Chang Chang ,  Yuan-Hung Chung

    IPC分类号： H01L29/06

    CPC分类号： H01L23/5225 ,  H01L23/552 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A seal ring structure for an integrated circuit includes a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise. A P+ region is provided in a P substrate and positioned under the second portion. A shallow trench isolation (STI) structure surrounds the P+ region and laterally extends underneath a conductive rampart of the second portion.

    摘要翻译： 用于集成电路的密封环结构包括沿着集成电路的周边设置的密封环，其中密封环被分成至少第一部分和第二部分，并且其中第二部分定位成面对并屏蔽模拟 和/或RF电路块。 P +区域设置在P基板中并且位于第二部分下方。 浅沟槽隔离（STI）结构围绕P +区域并且横向延伸在第二部分的导电栅栏之下。

    DUAL CONTACT ETCH STOP LAYER PROCESS
    15.
    发明申请
    DUAL CONTACT ETCH STOP LAYER PROCESS 审中-公开
    双重接触蚀刻停止层工艺

    公开(公告)号：US20090215277A1

    公开(公告)日：2009-08-27

    申请号：US12037089

    申请日：2008-02-26

    申请人： Tung-Hsing Lee ,  Ming-Tzong Yang ,  Ching-Chung Ko ,  Tien-Chang Chang ,  Yu-Tung Chang

    发明人： Tung-Hsing Lee ,  Ming-Tzong Yang ,  Ching-Chung Ko ,  Tien-Chang Chang ,  Yu-Tung Chang

    IPC分类号： H01L21/31

    CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L29/7843

    摘要： A dual CESL process includes: (1) providing a substrate having thereon a first device region, a second device region and a shallow trench isolation (STI) region between the first and second device regions; (2) forming a first-stress imparting film with a first stress over the substrate, wherein the first-stress imparting film does not cover the second device region; and (3) forming a second-stress imparting film with a second stress over the substrate, wherein the second-stress imparting film does not cover the first device region, an overlapped boundary between the first- and second-stress imparting films is created directly above the STI region, and wherein the overlapped boundary is placed in close proximity to the second device region in order to induce the first stress to a channel region thereof in a transversal direction.

    摘要翻译： 双CESL工艺包括：（1）提供其上具有第一和第二器件区域之间的第一器件区域，第二器件区域和浅沟槽隔离（STI）区域的衬底; （2）在所述基板上形成具有第一应力的第一应力赋予膜，其中所述第一应力赋予膜不覆盖所述第二器件区域; 和（3）在基板上形成具有第二应力的第二应力赋予膜，其中第二应力赋予膜不覆盖第一器件区域，直接产生第一和第二施加应力膜之间的重叠边界 在STI区域之上，并且其中重叠的边界被放置成紧邻第二器件区域，以便在横向方向上引起其沟道区域的第一应力。

    METHOD FOR FABRICATING EMBEDDED STATIC RANDOM ACCESS MEMORY
    17.
    发明申请
    METHOD FOR FABRICATING EMBEDDED STATIC RANDOM ACCESS MEMORY 有权
    嵌入式静态随机存取存储器的方法

    公开(公告)号：US20090023256A1

    公开(公告)日：2009-01-22

    申请号：US11779880

    申请日：2007-07-18

    申请人： Tung-Hsing Lee ,  Chien-Li Kuo ,  Yun-San Huang ,  Chih-Ming Su ,  Buo-Chin Hsu

    发明人： Tung-Hsing Lee ,  Chien-Li Kuo ,  Yun-San Huang ,  Chih-Ming Su ,  Buo-Chin Hsu

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/1104 ,  H01L27/105 ,  H01L27/1116

    摘要： The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask.

    摘要翻译： 本发明提供了一种制造嵌入式静态随机存取存储器的方法，包括提供半导体衬底; 在所述半导体衬底上限定逻辑区域和存储单元区域，并分别在所述逻辑区域和所述存储器单元区域中至少限定第一导电器件区域和至少第二导电器件区域; 在所述存储单元区域和所述逻辑区域中的所述第二导电器件区域上形成图案化掩模，并且暴露所述逻辑区域中的所述第一导电器件区域; 在所述逻辑区域中暴露的第一导电器件区域上执行第一导电离子注入工艺; 并去除图案化掩模。

    Semiconductor diode
    19.
    发明授权
    Semiconductor diode 有权
    半导体二极管

    公开(公告)号：US09373727B2

    公开(公告)日：2016-06-21

    申请号：US13168311

    申请日：2011-06-24

    申请人： Ming-Tzong Yang ,  Tung-Hsing Lee

    发明人： Ming-Tzong Yang ,  Tung-Hsing Lee

    IPC分类号： H01L21/70 ,  H01L29/861 ,  H01L29/417 ,  H01L29/45

    CPC分类号： H01L29/861 ,  H01L29/417 ,  H01L29/45

    摘要： A semiconductor diode includes a semiconductor substrate having a lightly doped region with a first conductivity type therein. A first heavily doped region with a second conductivity type opposite to the first conductivity type is in the lightly doped region. A second heavily doped region with the first conductivity type is in the lightly doped region and is in direct contact with the first heavily doped region. A first metal silicide layer is on the semiconductor substrate and is in direct contact with the first heavily doped region. A second metal silicide layer is on the semiconductor substrate and is in direct contact with the second heavily doped region. The second metal silicide layer is spaced apart from the first metal silicide layer.

    摘要翻译： 半导体二极管包括其中具有第一导电类型的轻掺杂区的半导体衬底。 具有与第一导电类型相反的第二导电类型的第一重掺杂区域在轻掺杂区域中。 具有第一导电类型的第二重掺杂区域在轻掺杂区域中并且与第一重掺杂区域直接接触。 第一金属硅化物层在半导体衬底上并且与第一重掺杂区域直接接触。 第二金属硅化物层在半导体衬底上并与第二重掺杂区域直接接触。 第二金属硅化物层与第一金属硅化物层间隔开。

    Integrated inductor
    20.
    发明授权
    Integrated inductor 有权
    集成电感

    公开(公告)号：US08860544B2

    公开(公告)日：2014-10-14

    申请号：US12493245

    申请日：2009-06-29

    申请人： Ching-Chung Ko ,  Tung-Hsing Lee ,  Kuei-Ti Chan ,  Tao Cheng ,  Ming-Tzong Yang

    发明人： Ching-Chung Ko ,  Tung-Hsing Lee ,  Kuei-Ti Chan ,  Tao Cheng ,  Ming-Tzong Yang

    IPC分类号： H01F5/00

    CPC分类号： H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well.

    摘要翻译： 集成电感器包括由钝化层顶部的铝层组成的绕组，其中铝层不延伸到钝化层中，并且具有不小于约2.0微米的厚度。 钝化层的厚度不小于约0.8微米。 通过从集成电感器中消除铜并增加钝化层的厚度，电感器结构的底表面与半导体衬底的主表面之间的距离增加，因此寄生衬底耦合可能会降低，Q因子 可以改进。 此外，铝层的增加的厚度也可以有助于改善Q因子。