公开(公告)号：US20060126412A1

公开(公告)日：2006-06-15

申请号：US11335697

申请日：2006-01-20

申请人： Yasuhiko Maki

发明人： Yasuhiko Maki

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/50012 ,  G11C11/41 ,  G11C29/16 ,  G11C29/50 ,  G11C2029/5002

摘要： An integrated circuit device of the invention, has a memory macro which during normal operation latches an input address in response to a control pulse and generates data output corresponding to the input address, and a test control circuit 22 which during testing performs memory macro characteristic tests. A ring oscillator is configured by connecting a prescribed number of stages comprising one or more memory macro units, having a memory macro and a pulse generation circuit which during testing generates a control pulse for tests in response to an input pulse, and the test control circuit measures the oscillation frequency or period of the ring oscillator.

摘要翻译： 本发明的集成电路装置具有存储器宏，其在正常操作期间响应于控制脉冲锁存输入地址并产生对应于输入地址的数据输出;以及测试控制电路22，其在测试期间执行存储器宏特性测试 。 环形振荡器通过连接包括具有存储器宏的一个或多个存储器宏单元的规定数量的级，并且在测试期间产生用于响应于输入脉冲进行测试的控制脉冲的脉冲生成电路来配置，并且测试控制电路 测量环形振荡器的振荡频率或周期。

公开(公告)号：US5477178A

公开(公告)日：1995-12-19

申请号：US213514

申请日：1994-03-16

申请人： Yasuhiko Maki

发明人： Yasuhiko Maki

IPC分类号： H01L21/82 ,  G11C7/10 ,  H01L21/822 ,  H01L27/04 ,  H03H11/26

CPC分类号： G11C7/1093 ,  G11C7/1051 ,  G11C7/1078

摘要： A data-hold timing adjustment circuit having resistance wires to which a power-supply voltage is supplied, formed along numerous flip-flops. MOS variable capacitors 3i and 4i (i=1 to n) are connected at one electrode to the data input end of the flip-flops and at another electrode to the resistance wires. The composite capacitance of the MOS capacitors becomes larger as the value of i increases, independent of the voltage level of the data input end of the flip-flops. When the potential of the data input end of the flip-flop shifts from a high/low level to a low/high level, this shift is delayed more as the value of i becomes larger, while the clock input to the flip-flop is delayed more as the value of i becomes larger.

摘要翻译： 具有沿许多触发器形成的具有供电电压的电阻线的数据保持定时调整电路。 MOS可变电容器3i和4i（i = 1至n）在一个电极处连接到触发器的数据输入端，并且在另一个电极处连接到电阻线。 随着i的值增加，MOS电容的复合电容变大，与触发器的数据输入端的电压电平无关。 当触发器的数据输入端的电位从高/低电平变化到低/高电平时，随着i的值变大，该移位被延迟更多，而向触发器输入的时钟是 延迟更多，因为i的值变大。

公开(公告)号：US20070201263A1

公开(公告)日：2007-08-30

申请号：US11494746

申请日：2006-07-28

申请人： Yasuhiko Maki

发明人： Yasuhiko Maki

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C11/413

摘要： Included are first and second inverters 1L, 1R, a first selection transistor N1 controlling a connection of an output terminal of the first inverter 1L to a bit line 11, and a second selection transistor N2 controlling a connection of an output terminal of the second inverter 1R to a bit line 12, wherein the first inverter 1L having a first load transistor P1 and a first drive transistor N3 and the second inverter 1R having a second load transistor P2 and a second drive transistor N4, function as a memory cell 1, and a ratio of a driving current quantity that can be outputted in an ON-state of the first drive transistor N3 to a driving current quantity that can be outputted in an ON-state of the first selection transistor N1, is larger than a first predetermined value.

摘要翻译： 包括第一和第二反相器1L，R1，控制第一反相器11L的输出端与位线11的连接的第一选择晶体管N 1和控制输出的连接的第二选择晶体管N 2 第二反相器1R的端子到位线12，其中第一反相器L1具有第一负载晶体管P 1和第一驱动晶体管N 3，第二反相器1R具有第二负载晶体管P 2和第二驱动 用作存储单元1的晶体管N 4，以及可以在第一驱动晶体管N 3的导通状态下输出的驱动电流量与可以在导通状态的导通状态下输出的驱动电流量的比率 第一选择晶体管N 1大于第一预定值。

公开(公告)号：US06501694B2

公开(公告)日：2002-12-31

申请号：US09972943

申请日：2001-10-10

申请人： Yasuhiko Maki

发明人： Yasuhiko Maki

IPC分类号： G11C700

CPC分类号： G11C7/12

摘要： Precharge circuits comprises PMOS transistors Q6 and Q7 each connected between a bit line and a power source potential VDD, PMOS transistors Q2, Q5, Q8 and Q11 connected between respective bit line pairs, and PMOS transistors Q21 and Q23 connected between respective adjacent bit lines of adjacent bit line pairs, wherein the gate electrodes of the PMOS transistors are each connected to a precharge control signal line PCG. The defect caused by omission of transistors from the prior art circuits is compensated by the PMOS transistors Q21 and Q23, each of which is required to be provided for two bit line pairs. With this and transistors of adjacent unit precharge circuits are arranged in plain symmetry, there is no need to provide transistors to be directly connected between bit lines *B2 and B3, and an average number of PMOS transistors for each bit line pair is less than 2.5.

摘要翻译： 预充电电路包括各自连接在位线与连接在各位线对之间的电源电位VDD，PMOS晶体管Q2，Q5，Q8和Q11之间的PMOS晶体管Q6和Q7以及连接在相应位线对之间的PMOS晶体管Q21和Q23 相邻位线对，其中PMOS晶体管的栅极电极各自连接到预充电控制信号线PCG。 由现有技术电路省略晶体管引起的缺陷由PMOS晶体管Q21和Q23补偿，每个PMOS晶体管Q21和Q23需要为两个位线对提供。 由此，相邻的单位预充电电路的晶体管以对称的方式排列，不需要提供要直接连接在位线B2和B3之间的晶体管，并且每个位线对的PMOS晶体管的平均数小于2.5 。

公开(公告)号：US6081444A

公开(公告)日：2000-06-27

申请号：US204278

申请日：1998-12-03

申请人： Yasuhiko Maki ,  Hiroshi Shimizu ,  Hiroshi Kagiwata

发明人： Yasuhiko Maki ,  Hiroshi Shimizu ,  Hiroshi Kagiwata

IPC分类号： H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  G11C11/00

CPC分类号： H01L27/1104

摘要： A static memory in which memory cells each have the components thereof laid out so that the area of each memory cell can be further reduced in compliance with improvement in technology of separating devices. The static memory includes CMOS memory cells each having two cross-coupled inverters, in each of which an n-channel transistor and p-channel transistor are connected in series with each other. At least one of the contacts used to cross-couple the two inverters is located in a region other than a region enclosed by the diffused sources and drains of the n-channel transistors and p-channel transistors included in the memory cell.

摘要翻译： 一种静态存储器，其中存储单元各自具有其组件布局，使得可以根据分离设备的技术的改进来进一步减小每个存储单元的面积。 静态存储器包括各自具有两个交叉耦合的反相器的CMOS存储单元，其中每个都具有n沟道晶体管和p沟道晶体管彼此串联连接。 用于交叉耦合两个反相器的触点中的至少一个位于由包括在存储单元中的n沟道晶体管和p沟道晶体管的扩散源和漏极所围绕的区域之外的区域中。

公开(公告)号：US4961170A

公开(公告)日：1990-10-02

申请号：US452421

申请日：1989-12-19

申请人： Fujitsu Limited ,  Yasuhiko Maki ,  Osamu Nomura

发明人： Fujitsu Limited ,  Yasuhiko Maki ,  Osamu Nomura

IPC分类号： G11C11/417 ,  G05F3/22 ,  G11C7/06 ,  G11C8/08 ,  G11C11/407 ,  H03K19/00 ,  H03K19/0944

CPC分类号： G05F3/22 ,  G11C7/062 ,  G11C8/08 ,  H03K19/0027 ,  H03K19/09448

摘要： A logic circuit improves a marginal voltage of a p-channel metal oxide semiconductor (MOS) transistor which is driven through a bipolar complementary metal oxide semiconductor (CMOS) gate. The logic circuit has a bipolar CMOS gate having a CMOS gate and output stage bipolar transistors for receiving an input signal through the CMOS gate, where the CMOS gate and the output stage bipolar transistors are driven by first and second power source voltages. The first power source voltage is higher than the second power source voltage and the output stage bipolar transistors output a signal as an output signal of the bipolar CMOS gate. A p-channel MOS transistor has a gate supplied with the output signal of the bipolar CMOS gate, a source supplied with a third power source voltage, and a drain from which an output signal of the logic circuit is outputted. The third power source voltage is a predetermined value lower than the first power source voltage and higher than the second power source voltage. As a result the turning OFF of the p-channel MOS transistor is guaranteed due to the improved marginal voltage.

公开(公告)号：US07411813B2

公开(公告)日：2008-08-12

申请号：US10976913

申请日：2004-11-01

申请人： Yasuhiko Maki

发明人： Yasuhiko Maki

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： In case that data are written in a flip-flop circuit by inverting the voltage to be supplied to a pair of write bit lines, the peak of the current waveform flowing in the pair of write bit lines is to be made gentler, whereby reduced power source noise and low power consumption should be achieved. To this end in a semiconductor device wherein flip-flop circuit for holding data, a memory cell including a transfer gate, a pair of write bit lines for writing data in the memory cell, are provided, in case that data are written in the flip-flop circuit by inverting the voltage to be supplied to the pair of write bit lines, the slew rate of the voltage to be supplied to the pair of write bit lines is made equal to predetermined value or less.

摘要翻译： 在通过将要提供给一对写入位线的电压反相来写入触发器电路的情况下，使在一对写入位线中流动的电流波形的峰值变得更平缓，由此降低功率 源噪声和低功耗应该实现。 为此，提供了用于保存数据的触发电路，包括传输门的存储单元，用于在存储单元中写入数据的一对写位线的半导体器件，在数据被写入翻转 通过将要提供给一对写位线的电压反相来提供给一对写位线的电压的转换速率等于或小于预定值。

公开(公告)号：US20070081407A1

公开(公告)日：2007-04-12

申请号：US11341429

申请日：2006-01-30

申请人： Yasuhiko Maki ,  Koji Shimosako

发明人： Yasuhiko Maki ,  Koji Shimosako

IPC分类号： G11C5/14

CPC分类号： G11C11/419 ,  G11C11/412

摘要： Each memory cell has a pair of inverters whose inputs and outputs are connected to each other and holds complementary data respectively in storage nodes which are outputs of the inverters. In a write operation during which the complementary data are written to the storage nodes respectively, the power control circuit sets a power supply voltage of the inverter having the storage node to which low level is written lower than a power supply voltage of the inverter having the storage node to which high level is written. Since power supply capability to the inverter having the storage node to which the low level is written lowers, the voltage of the storage node easily changes to the low level. That is, a write margin of a memory cell can be improved.

摘要翻译： 每个存储单元具有一对反相器，其输入和输出彼此连接并分别保存在作为反相器的输出的存储节点中的互补数据。 在将补充数据分别写入存储节点的写入操作中，功率控制电路设置具有写入低电平的存储节点的逆变器的电源电压低于具有该等级的逆变器的电源电压 写入高级别的存储节点。 由于具有写入低电平的存储节点的逆变器的电力供应能力降低，所以存储节点的电压容易变为低电平。 也就是说，可以提高存储单元的写入裕度。

公开(公告)号：US20060239094A1

公开(公告)日：2006-10-26

申请号：US11438447

申请日：2006-05-23

申请人： Yasuhiko Maki ,  Toshiyuki Uetake

发明人： Yasuhiko Maki ,  Toshiyuki Uetake

IPC分类号： G11C7/02

CPC分类号： H01L27/1104 ,  G11C7/06 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22 ,  G11C7/227 ,  G11C11/413

摘要： A semiconductor memory including a sense amplifier circuit for reading the data stored in memory cells and particularly to a semiconductor memory including a self-timing circuit for improving margin for reading data by controlling activation timing of the sense amplifier drive signal in accordance with characteristics of internal memory cells.

摘要翻译： 一种半导体存储器，包括用于读取存储在存储单元中的数据的读出放大器电路，特别是涉及包括用于通过根据内部特性控制读出放大器驱动信号的激活定时来提高读取数据的余量的半自动计时电路的半导体存储器 记忆细胞

公开(公告)号：US20060013036A1

公开(公告)日：2006-01-19

申请号：US10976913

申请日：2004-11-01

申请人： Yasuhiko Maki

发明人： Yasuhiko Maki

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： In case that data are written in a flip-flop circuit by inverting the voltage to be supplied to a pair of write bit lines, the peak of the current waveform flowing in the pair of write bit lines is to be made gentler, whereby reduced power source noise and low power consumption should be achieved. To this end in a semiconductor device wherein flip-flop circuit for holding data, a memory cell including a transfer gate, a pair of write bit lines for writing data in the memory cell, are provided, in case that data are written in the flip-flop circuit by inverting the voltage to be supplied to the pair of write bit lines, the slew rate of the voltage to be supplied to the pair of write bit lines is made equal to predetermined value or less.

摘要翻译： 在通过将要提供给一对写入位线的电压反相来写入触发器电路的情况下，使在一对写入位线中流动的电流波形的峰值变得更平缓，由此降低功率 源噪声和低功耗应该实现。 为此，提供了用于保存数据的触发电路，包括传输门的存储单元，用于在存储单元中写入数据的一对写位线的半导体器件，在数据被写入翻转 通过将要提供给一对写位线的电压反相来提供给一对写位线的电压的转换速率等于或小于预定值。