公开(公告)号：US20170069750A9

公开(公告)日：2017-03-09

申请号：US14224043

申请日：2014-03-24

Applicant: Yeeheng Lee ,  Yongping Ding ,  Xiaobin Wang

Inventor： Yeeheng Lee ,  Yongping Ding ,  Xiaobin Wang

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

Abstract translation: 具有多个晶体管的半导体器件包括具有非对称栅极的晶体管的端接区域。

公开(公告)号：US08803251B2

公开(公告)日：2014-08-12

申请号：US13135982

申请日：2011-07-19

Applicant: Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

Inventor： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC: H01L29/06 ,  H01L21/76

CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

Abstract translation: 本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

公开(公告)号：US08587061B2

公开(公告)日：2013-11-19

申请号：US13559502

申请日：2012-07-26

Applicant: Yeeheng Lee ,  Yongping Ding ,  John Chen

Inventor： Yeeheng Lee ,  Yongping Ding ,  John Chen

IPC: H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/782

Abstract: A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench.

Abstract translation: 功率MOSFET器件及其制造方法包括以下步骤：在接触沟槽的底部的中间区域选择性地沉积第一导电材料，并与光掺杂的N型外延层接触以形成肖特基结，并沉积第二导电材料 导电材料在接触沟槽的侧壁和底角处并与P型重掺杂体区域接触以形成欧姆结。 第一和第二导电材料可以分别优化欧姆接触和肖特基接触的性能而不折不扣。 同时，接触沟槽的角部被P型重掺杂区域围绕，从而有效地减少了在接触沟槽的拐角处积聚的漏电流。

公开(公告)号：US20110316076A1

公开(公告)日：2011-12-29

申请号：US12826591

申请日：2010-06-29

Applicant: Yeeheng Lee ,  Yongping Ding ,  John Chen

Inventor： Yeeheng Lee ,  Yongping Ding ,  John Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/782

Abstract: A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench.

Abstract translation: 功率MOSFET器件及其制造方法包括以下步骤：在接触沟槽的底部的中间区域选择性地沉积第一导电材料，并与光掺杂的N型外延层接触以形成肖特基结，并沉积第二导电材料 导电材料在接触沟槽的侧壁和底角处并与P型重掺杂体区域接触以形成欧姆结。 第一和第二导电材料可以分别优化欧姆接触和肖特基接触的性能而不折不扣。 同时，接触沟槽的角部被P型重掺杂区域围绕，从而有效地减少了在接触沟槽的拐角处积聚的漏电流。

公开(公告)号：US20160372542A9

公开(公告)日：2016-12-22

申请号：US14329936

申请日：2014-07-12

Applicant: Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

Inventor： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC: H01L29/06 ,  H01L21/761 ,  H01L29/78

CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

公开(公告)号：US20160013267A1

公开(公告)日：2016-01-14

申请号：US14329936

申请日：2014-07-12

Applicant: Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

Inventor： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC: H01L29/06 ,  H01L21/761 ,  H01L29/78

CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

Abstract translation: 本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

公开(公告)号：US20150060936A1

公开(公告)日：2015-03-05

申请号：US14011078

申请日：2013-08-27

Applicant: Yongping Ding ,  Sik Lui ,  Madhur Bobde ,  Lei Zhang ,  Jongoh Kim ,  John Chen

Inventor： Yongping Ding ,  Sik Lui ,  Madhur Bobde ,  Lei Zhang ,  Jongoh Kim ,  John Chen

IPC: H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/66666 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches formed at a top portion of the semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction each having a nonlinear portion comprising a sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

Abstract translation: 本发明公开了一种设置在半导体衬底中的半导体功率器件。 半导体功率器件包括形成在半导体衬底的顶部的多个沟槽，其沿着纵向方向横向跨越半导体衬底延伸，每个具有非线性部分，该非线性部分包括垂直于沟槽的纵向方向的侧壁，并且垂直向下延伸 顶面到沟槽底面。 半导体功率器件还包括设置在沟槽底表面下方的沟槽底部掺杂剂区域和沿着垂直侧壁设置的侧壁掺杂剂区域，其中侧壁掺杂剂区域沿着沟槽的垂直侧壁垂直向下延伸以到达沟槽底部掺杂剂区域， 将沟槽底部掺杂剂区域拾取到半导体衬底的顶表面。

公开(公告)号：US20140027841A1

公开(公告)日：2014-01-30

申请号：US13561523

申请日：2012-07-30

Applicant: Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

Inventor： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US20130228857A1

公开(公告)日：2013-09-05

申请号：US13411422

申请日：2012-03-02

Applicant: Yeeheng Lee ,  Yongping Ding ,  Xiaobin Wang

Inventor： Yeeheng Lee ,  Yongping Ding ,  Xiaobin Wang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

Abstract translation: 具有多个晶体管的半导体器件包括具有非对称栅极的晶体管的端接区域。

公开(公告)号：US09887283B2

公开(公告)日：2018-02-06

申请号：US13892191

申请日：2013-05-10

Applicant: Yongping Ding ,  Lei Zhang ,  Hong Chang ,  Jongoh Kim ,  John Chen

Inventor： Yongping Ding ,  Lei Zhang ,  Hong Chang ,  Jongoh Kim ,  John Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/78 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7827

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.