Abstract:
An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.
Abstract:
An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material.
Abstract:
The present disclosure provides a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.
Abstract:
A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database.
Abstract:
The present disclosure describes an OPC method of preparing data for forming a mask. The method includes setting a plurality of dissection points at the main feature and further includes setting a target point at the main feature. The method includes arranging the two dissection points crossing the main feature symmetrically each other. The method includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer. The method includes dividing the main feature into a plurality of segments using the dissection points. The method includes performing an OPC convergence simulation to a target point. The method includes correcting the segments belonging to an ambit of the target point and further includes correcting the segment shared by two ambits.
Abstract:
The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.
Abstract:
The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having an main feature, the main feature including two corners and an edge spanning between the two corners; performing a feature adjustment to the edge; performing a dissection to the edge such that the edge is divided to include two corner segments and one center segment between the two corner segments; performing a first optical proximity correction (OPC) to the main feature for a center target associated with the center segment; thereafter, performing a second OPC to the main feature for two corner targets associated with the corner segments; and thereafter, performing a third OPC to main feature for the center target, resulting in a modified design layout.
Abstract:
The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having an main feature, the main feature including two corners and an edge spanning between the two corners; performing a feature adjustment to the edge; performing a dissection to the edge such that the edge is divided to include two corner segments and one center segment between the two corner segments; performing a first optical proximity correction (OPC) to the main feature for a center target associated with the center segment; thereafter, performing a second OPC to the main feature for two corner targets associated with the corner segments; and thereafter, performing a third OPC to main feature for the center target, resulting in a modified design layout.