公开(公告)号：US20210406145A1

公开(公告)日：2021-12-30

申请号：US17004589

申请日：2020-08-27

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kelley ,  Paul Moyer

IPC: G06F11/30 ,  G06F11/34 ,  G06F11/07 ,  G06F12/0891 ,  G06F12/0804

Abstract: An electronic device includes a cache with a cache controller and a cache memory. The electronic device also includes a cache policy manager. The cache policy manager causes the cache controller to use two or more cache policies for cache operations in each of multiple test regions in the cache memory, with different configuration values for the two or more cache policies being used in each test region. The cache policy manager selects a selected configuration value for at least one cache policy of the two or more cache policies based on performance metrics for cache operations while using the different configuration values for the two or more cache policies in the test regions. The cache policy manager causes the cache controller to use the selected configuration value when using the at least one cache policy for cache operations in a main region of the cache memory.

公开(公告)号：US11210234B2

公开(公告)日：2021-12-28

申请号：US16669973

申请日：2019-10-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul Moyer ,  John Kelley

IPC: G06F12/12

Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.

公开(公告)号：US20220141011A1

公开(公告)日：2022-05-05

申请号：US17089493

申请日：2020-11-04

Applicant: Advanced Micro Devices, Inc.

Inventor： David A Kaplan ,  Paul Moyer

IPC: H04L9/08 ,  G06F7/58

Abstract: A computing system may implement a split random number generator that may use a random number generator to generate and store seed values in a memory for retrieval and use by one or more core processors to generate random numbers for secure processes within each core processor.

公开(公告)号：US11182306B2

公开(公告)日：2021-11-23

申请号：US15359829

申请日：2016-11-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul Moyer

IPC: G06F12/123 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/12

Abstract: A processor applies a software hint policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies a different software hint policy for data associated with cache entries in each region of the cache. One test region applies a software hint policy under which software hints are followed. The other test region applies a software hint policy under which software hints are ignored. One of the software hint policies is selected for application to a non-test region of the cache.

公开(公告)号：US20210182214A1

公开(公告)日：2021-06-17

申请号：US16718162

申请日：2019-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul Moyer

IPC: G06F12/122 ,  G06F12/0897 ,  G06F12/0862

Abstract: A method includes recording a first set of cache performance metrics for a target cache, for each prefetch request of a plurality of prefetch requests received at the target cache, determining based on the first set of cache performance metrics a relative priority of the prefetch request relative to a threshold priority level for the target cache, for each low-priority prefetch request of the plurality of prefetch requests, redirecting the low-priority prefetch request to a first lower-level cache in response to determining that a priority of the low-priority prefetch request is less than the threshold priority level for the target cache, and for each high-priority prefetch request of the plurality of prefetch requests, storing prefetch data in the target cache according to the high-priority prefetch request in response to determining that a priority of the high-priority prefetch request is greater than the threshold priority level for the target cache.

公开(公告)号：US10528483B2

公开(公告)日：2020-01-07

申请号：US15790743

申请日：2017-10-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul Moyer

IPC: G06F12/0811 ,  G06F12/0895 ,  G06F12/128

Abstract: A system includes one or more processor cores and a cache hierarchy. The cache hierarchy includes a first-level cache, a second-level cache, and a third-level cache. The cache hierarchy further includes cache hierarchy control logic configured to implement a caching policy in which each cacheline cached in the first-level cache has a copy of the cacheline cached in at least one of the second-level cache and the third-level cache. The caching policy further provides that an eviction of a cacheline from the second-level cache does not trigger an eviction of a copy of that cacheline from the first-level cache, and that an eviction of a cacheline from the third-level cache triggers the cache hierarchy control logic to evict a copy of that cacheline from the first-level cache when the cacheline is not present in the second-level cache.

公开(公告)号：US20180143911A1

公开(公告)日：2018-05-24

申请号：US15359829

申请日：2016-11-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul Moyer

IPC: G06F12/123 ,  G06F12/0862 ,  G06F12/0891

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/502 ,  G06F2212/6028

Abstract: A processor applies a software hint policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies a different software hint policy for data associated with cache entries in each region of the cache. One test region applies a software hint policy under which software hints are followed. The other test region applies a software hint policy under which software hints are ignored. One of the software hint policies is selected for application to a non-test region of the cache.

公开(公告)号：US11868777B2

公开(公告)日：2024-01-09

申请号：US17123270

申请日：2020-12-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kalamatianos ,  Michael T. Clark ,  Marius Evers ,  William L. Walker ,  Paul Moyer ,  Jay Fleischman ,  Jagadish B. Kotra

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/30181 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30138 ,  G06F9/3834 ,  G06F9/3877 ,  G06F9/52

Abstract: Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.

公开(公告)号：US11803473B2

公开(公告)日：2023-10-31

申请号：US17521483

申请日：2021-11-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kelley ,  Paul Moyer

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0868

CPC classification number: G06F12/084 ,  G06F12/0811 ,  G06F12/0868

Abstract: Systems and techniques for dynamic selection of policy that determines whether copies of shared cache lines in a processor core complex are to be stored and maintained in a level 3 (L3) cache of the processor core complex are based on one or more cache line sharing parameters or based on a counter that tracks L3 cache misses and cache-to-cache (C2C) transfers in the processor core complex, according to various embodiments. Shared cache lines are shared between processor cores or between threads. By comparing either the cache line sharing parameters or the counter to corresponding thresholds, a policy is set which defines whether copies of shared cache lines at such indices are to be retained in the L3 cache.

公开(公告)号：US11467937B2

公开(公告)日：2022-10-11

申请号：US17004589

申请日：2020-08-27

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kelley ,  Paul Moyer

IPC: G06F11/30 ,  G06F11/34 ,  G06F12/0804 ,  G06F12/0891 ,  G06F11/07

Abstract: An electronic device includes a cache with a cache controller and a cache memory. The electronic device also includes a cache policy manager. The cache policy manager causes the cache controller to use two or more cache policies for cache operations in each of multiple test regions in the cache memory, with different configuration values for the two or more cache policies being used in each test region. The cache policy manager selects a selected configuration value for at least one cache policy of the two or more cache policies based on performance metrics for cache operations while using the different configuration values for the two or more cache policies in the test regions. The cache policy manager causes the cache controller to use the selected configuration value when using the at least one cache policy for cache operations in a main region of the cache memory.