公开(公告)号：US11961831B2

公开(公告)日：2024-04-16

申请号：US17408297

申请日：2021-08-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/48141 ,  H01L2224/48227

Abstract: An electronic package, a semiconductor package structure and a method for manufacturing the same are provided. The electronic package includes a carrier, a first electronic component, an electrical extension structure, and an encapsulant. The carrier has a first face and a second face opposite to the first face. The first electronic component is adjacent to the first face of the carrier. The electrical extension structure is adjacent to the first face of the carrier and defines a space with the carrier for accommodating the first electronic component, the electrical extension structure is configured to connect the carrier with an external electronic component. The encapsulant encapsulates the first electronic component and at least a portion of the electrical extension structure.

公开(公告)号：US11881448B2

公开(公告)日：2024-01-23

申请号：US17315067

申请日：2021-05-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt ,  Kay Stefan Essig

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4814 ,  H01L23/49822

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first package and a second package. The first package includes a first substrate, an electronic component, a trace layer, and a first conductive structure. The first substrate has a first surface and a second surface opposite to the first surface. The electronic component is embedded in the first substrate. The trace layer has an uppermost conductive layer embedded in the first substrate and exposed from the first surface of the first substrate. The first conductive structure electrically connects the trace layer to the second surface of the first substrate. The second package is disposed on the first surface of the first substrate of the first package.

公开(公告)号：US11830799B2

公开(公告)日：2023-11-28

申请号：US17223932

申请日：2021-04-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/66 ,  H01L21/56 ,  H01Q1/22 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/49822 ,  H01L23/552 ,  H01L23/66 ,  H01Q1/2283 ,  H01L2223/6677

Abstract: A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a dielectric layer, an electronic component, a first conductive layer, and a conductive element. The dielectric layer has a first surface and a second surface opposite to the first surface. The electronic component is embedded in the dielectric layer. The first conductive layer is embedded in the dielectric layer and adjacent to the first surface of the dielectric layer. The conductive element is disposed on the first surface of the dielectric layer and in contact with the first conductive layer.

公开(公告)号：US11616007B2

公开(公告)日：2023-03-28

申请号：US17066411

申请日：2020-10-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt ,  Kay Stephan Essig

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

Abstract: An electronic package and method for manufacturing the same are provided. The electronic package includes a substrate and a wetting layer. The substrate includes a plurality of conductive step structures each including a first portion and a second portion. The first portion has a first bottom surface, a first outer surface and a first inner surface. The second portion has a second bottom surface, a second outer surface and a second inner surface, wherein the second portion partially exposes the first bottom surface. The wetting layer at least covers the second bottom surface, the second outer surface and the second inner surface of the second portion of each of the conductive step structures.

公开(公告)号：US11462484B2

公开(公告)日：2022-10-04

申请号：US17066408

申请日：2020-10-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt ,  Kay Stephan Essig

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

Abstract: An electronic package and manufacturing method thereof are provided. The electronic package includes a substrate, a first encapsulant, a wettable flank and a shielding layer. The substrate includes a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface. The first encapsulant is disposed on the first surface of the substrate. The wettable flank is exposed from the side surface of the substrate. The shielding layer covers a side surface of the first encapsulant, wherein on the side surface of the substrate, the shielding layer is spaced apart from the wettable flank.

公开(公告)号：US11322428B2

公开(公告)日：2022-05-03

申请号：US16700761

申请日：2019-12-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt

IPC: H01L23/48 ,  H01L23/482 ,  H01L23/31 ,  H01L21/762 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor device package includes a substrate, a first semiconductor die, a conductive via, a first contact pad and a second contact pad. The substrate includes a first surface, and a second surface opposite to the first surface, the substrate defines a cavity through the substrate. The first semiconductor die is disposed in the cavity, wherein the first semiconductor die includes an active surface adjacent to the first surface, and an inactive surface. The conductive via penetrates through the substrate. The first contact pad is exposed from the active surface of the first semiconductor die and adjacent to the first surface of the substrate. The second contact pad is disposed on the first surface of the substrate, wherein the second contact pad is connected to a first end of the conductive via.

公开(公告)号：US10978312B2

公开(公告)日：2021-04-13

申请号：US16403393

申请日：2019-05-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt ,  Kay Stefan Essig

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/552 ,  H01L21/56 ,  H01Q1/22 ,  H01Q1/52 ,  H01L25/18 ,  H01L25/04 ,  H01L25/16

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and a second surface opposite to the first surface, an encapsulant, and an antenna. The encapsulant is disposed on the first surface of the carrier. The antenna is disposed on the encapsulant. The antenna includes a seed layer and a conductive layer.

公开(公告)号：US10217728B2

公开(公告)日：2019-02-26

申请号：US15359403

申请日：2016-11-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl Appelt ,  Kay Stefan Essig ,  You-Lung Yen

IPC: H01L23/02 ,  H01L25/10 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor die, a first encapsulant, a first redistribution layer, a second encapsulant and a patterned conductive layer. The first encapsulant encloses the first semiconductor die and has a top surface and a lateral surface. The first redistribution layer is disposed on the top surface of the first encapsulant and electrically connected to the first semiconductor die, wherein a portion of the first redistribution layer is exposed from the lateral surface of the first encapsulant. The second encapsulant covers the first encapsulant and the first redistribution layer. The patterned conductive layer is disposed on at least one of the lateral surface of the first encapsulant or a lateral surface of the second encapsulant, and is electrically connected to the first redistribution layer.

公开(公告)号：US20140346670A1

公开(公告)日：2014-11-27

申请号：US14453139

申请日：2014-08-06

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

IPC: H01L23/00 ,  H01L23/28

CPC classification number: H01L24/14 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/49155 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

公开(公告)号：US08884424B2

公开(公告)日：2014-11-11

申请号：US14033673

申请日：2013-09-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

IPC: H01L23/12 ,  H01L23/053 ,  H01L21/56 ,  H01L23/522 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L23/29 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/49155 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

Abstract translation: 多层衬底包括第一外部导电图案化层，暴露第一外部导电图案化层的一部分以限定第一组焊盘的第一绝缘层，第二外部导电图案化层和暴露部分第一绝缘层的第二绝缘层 第二外导电图案层以限定第二组焊盘。 多层基板还包括内层，每层具有内部导电图案层，邻近内部导电图案化层形成的多个内部导电柱和内部电介质层，其中内部导电图案层和内部导电柱嵌入内部 电介质层和每个内部导电柱的顶表面从内部电介质层露出。