公开(公告)号：US11262197B2

公开(公告)日：2022-03-01

申请号：US16683117

申请日：2019-11-13

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Ying-Chung Chen ,  Hsun-Wei Chan ,  Lu-Ming Lai ,  Kuang-Hsiung Chen

IPC分类号： G01C3/08

摘要： An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.

公开(公告)号：US10446411B2

公开(公告)日：2019-10-15

申请号：US16102527

申请日：2018-08-13

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Yu-Tzu Peng

IPC分类号： H01L23/48 ,  H01L21/44 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H01L23/31 ,  H05K1/14 ,  H05K3/28 ,  H01L23/538

摘要： A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.

公开(公告)号：US10103110B2

公开(公告)日：2018-10-16

申请号：US15873784

申请日：2018-01-17

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tien-Szu Chen ,  Sheng-Ming Wang ,  Kuang-Hsiung Chen ,  Yu-Ying Lee

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

摘要： A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units which comprise a substrate unit; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures which comprise a semiconductor package structure comprising the substrate unit, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.

公开(公告)号：US20160284659A1

公开(公告)日：2016-09-29

申请号：US14667317

申请日：2015-03-24

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tien-Szu CHEN ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee

IPC分类号： H01L23/00 ,  H05K1/11 ,  H05K3/10 ,  H01L23/31

CPC分类号： H01L24/17 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3157 ,  H01L24/48 ,  H01L24/49 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48245 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/1511 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/10 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

摘要： The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure and a dielectric structure. The conductive structure has a first conductive surface and a second conductive surface opposite to the first conductive surface. The dielectric structure covers at least a portion of the conductive structure, and has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The first conductive surface does not protrude from the first dielectric surface, and the second conductive surface is recessed from the second dielectric surface. The dielectric structure includes, or is formed from, a photo-sensitive resin, and the dielectric structure defines a dielectric opening in the second dielectric surface to expose a portion of the second conductive surface.

摘要翻译： 本公开涉及一种半导体衬底结构，半导体封装及其制造方法。 半导体衬底结构包括导电结构和电介质结构。 导电结构具有与第一导电表面相对的第一导电表面和第二导电表面。 电介质结构覆盖导电结构的至少一部分，并且具有与第一电介质表面相对的第一电介质表面和第二电介质表面。 第一导电表面不从第一电介质表面突出，并且第二导电表面从第二电介质表面凹陷。 电介质结构包括或由感光树脂形成，并且电介质结构在第二电介质表面中限定电介质开口以暴露第二导电表面的一部分。

公开(公告)号：US20140308778A1

公开(公告)日：2014-10-16

申请号：US14313046

申请日：2014-06-24

申请人： ADVANCED SEMICONDUCTOR ENGINEERING, INC.

发明人： Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Hsiang-Ming Feng ,  Bing-Yun Cheng

IPC分类号： H01L21/56

CPC分类号： H01L21/561 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/97 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00

摘要： An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices is attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.

摘要翻译： 制造半导体器件封装的方法的实施例包括散热器矩阵和衬底。 多个半导体器件附接到基板。 然后，在散热片基板和基板之间形成封装体，其中封装体封装半导体器件。 然后，形成多个第一切割槽，其中第一切割槽延伸穿过散热器矩阵并且部分地延伸到包装主体中。 然后，形成多个第二切割槽，其中第二切割槽延伸穿过基板并通过封装主体延伸到第一切割槽，从而将散热器矩阵和基板分离成多个单独的半导体器件封装。

公开(公告)号：US20140021636A1

公开(公告)日：2014-01-23

申请号：US14033673

申请日：2013-09-23

申请人： ADVANCED SEMICONDUCTOR ENGINEERING, INC.

发明人： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

IPC分类号： H01L23/522

CPC分类号： H01L24/14 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/49155 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

摘要翻译： 多层衬底包括第一外部导电图案化层，暴露第一外部导电图案化层的一部分以限定第一组焊盘的第一绝缘层，第二外部导电图案化层和暴露部分第一绝缘层的第二绝缘层 第二外导电图案层以限定第二组焊盘。 多层基板还包括内层，每层具有内部导电图案层，邻近内部导电图案化层形成的多个内部导电柱和内部电介质层，其中内部导电图案层和内部导电柱嵌入内部 电介质层和每个内部导电柱的顶表面从内部电介质层露出。

公开(公告)号：US10573624B2

公开(公告)日：2020-02-25

申请号：US16194265

申请日：2018-11-16

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  I-Cheng Wang ,  Wun-Jheng Syu

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/24 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L23/498

摘要： A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.

公开(公告)号：US10049893B2

公开(公告)日：2018-08-14

申请号：US15453656

申请日：2017-03-08

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Yu-Tzu Peng

IPC分类号： H01L23/48 ,  H01L21/44 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

摘要： A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first surface and a second surface opposite the first surface. The pad has a first portion and a second portion on the first surface of the substrate. The first isolation layer is disposed on the first surface and covers the first portion of the pad, and the first isolation layer has a top surface. The interconnection layer is disposed on the second portion of the pad and has a top surface. The conductive post is disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer. The top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.

公开(公告)号：US10002843B2

公开(公告)日：2018-06-19

申请号：US14667317

申请日：2015-03-24

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/52 ,  H01L23/31 ,  H05K3/20 ,  H01L23/00 ,  H05K1/11 ,  H05K3/10

CPC分类号： H01L24/17 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/49 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48245 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/1511 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/10 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

摘要： The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure and a dielectric structure. The conductive structure has a first conductive surface and a second conductive surface opposite to the first conductive surface. The dielectric structure covers at least a portion of the conductive structure, and has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The first conductive surface does not protrude from the first dielectric surface, and the second conductive surface is recessed from the second dielectric surface. The dielectric structure includes, or is formed from, a photo-sensitive resin, and the dielectric structure defines a dielectric opening in the second dielectric surface to expose a portion of the second conductive surface.

公开(公告)号：US09984989B2

公开(公告)日：2018-05-29

申请号：US14855849

申请日：2015-09-16

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tien-Szu Chen ,  Sheng-Ming Wang ,  Kuang-Hsiung Chen ,  Yu-Ying Lee

IPC分类号： H01L23/49 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L2224/13012 ,  H01L2224/13025 ,  H01L2224/1412 ,  H01L2224/73204 ,  H01L2924/15313 ,  H01L2924/3512

摘要： A semiconductor substrate includes an insulating layer, a first conductive patterned layer disposed adjacent to a first surface of the insulating layer, and conductive bumps disposed on the first conductive patterned layer. Each conductive bump has a first dimension along a first direction and a second dimension along a second direction perpendicular to the first direction, and the first dimension is greater than the second dimension. A semiconductor package structure includes the semiconductor substrate, at least one die electrically connected to the conductive bumps, and a molding compound encapsulating the conductive bumps.