公开(公告)号：US09628211B1

公开(公告)日：2017-04-18

申请号：US14745025

申请日：2015-06-19

Applicant: Amazon Technologies, Inc.

Inventor： Gil Stoler ,  Yaniv Shapira

IPC: H04J3/06 ,  H04J3/14

CPC classification number: H04J3/0691 ,  G06F1/06 ,  G06F1/12 ,  H03K23/68 ,  H04J3/0635 ,  H04J3/0658 ,  H04J3/0697

Abstract: A clock generator for generating a clock equivalent to a target clock which is an input clock divided by a non-integer ratio is disclosed. The clock generator comprises a clock divider configured to receive the input clock and divide the input clock with a reconfigurable dividing ratio; and a control circuit controlling operations of the clock divider to divide the input clock by a first dividing ratio to generate a first number of cycles of a first clock in a frame, and divide the input clock by a second dividing ratio to generate a second number of cycles of a second clock in the frame, wherein a difference between a period of the frame and a cumulative time of the first number of cycles of the first clock and the second number of cycles of the second clock is less than a threshold value.

公开(公告)号：US20210157381A1

公开(公告)日：2021-05-27

申请号：US16698525

申请日：2019-11-27

Applicant: Amazon Technologies, Inc.

Inventor： Larisa Goffman-Vinopal ,  Udi Sherel ,  Anat Arbely ,  Yaniv Shapira

IPC: G06F1/324 ,  G06F1/08

Abstract: A method for managing clock frequency in a multi-core integrated circuit includes determining a minimum allowable operating clock frequency and a maximum allowable operating clock frequency for an integrated circuit having a plurality of processor cores. A plurality of clock sources is configured to provide a corresponding plurality of clock frequencies between the minimum allowable operating clock frequency and the maximum allowable operating clock frequency. A total number of active processor cores is determined. If it is determined that all of the plurality the processor cores are active, all active processor cores are operated at the minimum allowable operating clock frequency. If it is determined that the total number of active processor cores is lower than a threshold number, the clock frequency of one or more active processor cores is increased based on available electrical current budget.

公开(公告)号：US11003616B1

公开(公告)日：2021-05-11

申请号：US15635078

申请日：2017-06-27

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Adi Habusha ,  Yaniv Shapira ,  Daniel Joseph Grey

IPC: G06F13/42 ,  G06F13/40

Abstract: In a computer comprising a plurality of integrated circuits (ICs), each IC may be connected to all other ICs via a respective point-to-point interconnect. A source IC divides the data to be transmitted to a destination IC for a transaction to generate multiple data cells so that each data cell includes a different portion of the data. The source IC transmits one of the data cells to the destination IC and remaining data cells to intermediate ICs, wherein an intermediate IC is an IC other than the source IC or the destination IC. The intermediate ICs forward the remaining data cells to the destination IC.

公开(公告)号：US10747258B1

公开(公告)日：2020-08-18

申请号：US15445747

申请日：2017-02-28

Applicant: Amazon Technologies, Inc.

Inventor： Eyal Freund ,  Yaniv Shapira

IPC: G06F1/12 ,  H03K3/03

Abstract: A semiconductor device includes a system clock signal having a system clock period and a digital ring oscillator (DRO) cluster having DRO cells. Each of the DRO cells is disposed at a different location in the semiconductor device for producing a local ring oscillator clock signal. The local ring oscillator clock signal has a ring oscillator clock period that is shorter than the system clock period. The DRO cluster is configured to measure respective ring oscillator clock count in each of the DRO cells during a time window synchronized to the system clock.

公开(公告)号：US10691576B1

公开(公告)日：2020-06-23

申请号：US15716319

申请日：2017-09-26

Applicant: Amazon Technologies, Inc.

Inventor： Yaniv Shapira ,  Gil Stoler ,  Adi Habusha

IPC: G06F11/36 ,  G01R31/317 ,  G06F11/263 ,  G01R31/3177 ,  G06F11/22 ,  G06F11/267

Abstract: An integrated circuit can include a functional unit and a local debug unit. The local debug unit can include a trace buffer, and the local debug unit is configured to track and store operation information of the functional unit in the trace buffer. The integrated circuit can also include a global debug unit coupled to the local debug unit. The integrated circuit is configured to send a debug reset command to reset the functional unit, without sending the debug reset command to the local debug unit, thereby retaining information stored in the trace buffer. The integrated circuit is also configured to send a power-up reset command to reset the local debug unit and the functional unit, thereby causing the local debug unit to clear the trace buffer.

公开(公告)号：US10044456B1

公开(公告)日：2018-08-07

申请号：US15489583

申请日：2017-04-17

Applicant: Amazon Technologies, Inc.

Inventor： Gil Stoler ,  Yaniv Shapira

IPC: H04J3/06 ,  G06F1/12 ,  G06F1/06

Abstract: A clock generator for generating a target clock with a frequency equal to the frequency of an input clock divided by a non-integer ratio is disclosed. The clock generator comprises a clock divider. The clock divider is configured to divide the input clock by a first dividing ratio during a first portion of a frame period to generate a first clock slower than the target clock, and divide the input clock by a second dividing ratio during a second portion of the frame period to generate a second clock faster than the target clock. A difference between the first dividing ratio and the second dividing ratio is 0.5 or 1. In some embodiments, the first dividing ratio and the second dividing ration are integers closest to the non-integer ratio.

公开(公告)号：US11960392B1

公开(公告)日：2024-04-16

申请号：US17643127

申请日：2021-12-07

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Dan Saad ,  Yaniv Shapira ,  Erez Izenberg

IPC: G06F13/14 ,  G06F9/46 ,  G06F12/02 ,  G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G11C11/408

CPC classification number: G06F12/0238 ,  G06F9/467 ,  G06F12/0292 ,  G06F13/1621 ,  G06F13/38 ,  G06F13/4221 ,  G11C11/4087

Abstract: A first configurable address decoder can be coupled between a source node and a first interconnect fabric, and a second address decoder can be coupled between the first interconnect fabric and a second interconnect fabric. The first address decoder can be configured with a first address mapping table that can map a first set of address ranges to a first set of target nodes connected to the first interconnect fabric. The second address decoder can be configured with a second address mapping table that can map a second set of address ranges to a second set of target nodes connected to the second interconnect fabric. The second address decoder can be part of the first set of target nodes. The first address decoder and the second address decoder can be configured or re-configured to determine different routes for a transaction from the source node to a target node in the second set of target nodes via the first and second interconnect fabrics.

公开(公告)号：US11640366B1

公开(公告)日：2023-05-02

申请号：US17457812

申请日：2021-12-06

Applicant: Amazon Technologies, Inc.

Inventor： Dan Saad ,  Guy Nakibly ,  Yaniv Shapira ,  Aviv Bonomo ,  Moshe Gutman

IPC: G06F13/362 ,  G06F13/42 ,  G06F13/40 ,  G06F15/78 ,  G06F9/46

Abstract: An address decoder for a source node in a multi-chip system is disclosed, which can perform parallel decoding steps to determine whether a transaction from the source node is addressed to a target node in a local integrated circuit (IC) or a remote IC, and whether the source node is allowed to access that target node. Based on the outcome of both the decoding steps, the transaction can be either blocked by the address decoder, or routed to the target node. If the transaction is addressed to the remote IC, but the source node is not allowed to access the target node on the remote IC, the transaction can be terminated by the address decoder in the local IC.

公开(公告)号：US10740466B1

公开(公告)日：2020-08-11

申请号：US15280897

申请日：2016-09-29

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Matthew Shawn Wilson ,  Eric Jason Brandwine ,  Anthony Nicholas Liguori ,  Yaniv Shapira ,  Mark Bradley Davis ,  Adi Habusha

IPC: G06F15/177 ,  G06F21/57 ,  G06F9/4401 ,  G06F21/72 ,  H04L9/06

Abstract: Interfaces of a compute node on a printed circuit board can be secured by obfuscating the information communicated over the interfaces. Data to be communicated between the compute node and a device on the printed circuit board using an interface can be encrypted, and an address corresponding to the data to be communicated can be scrambled. In addition, the compute node can be the root of trust which can provide secure boot of different components using an on-chip mechanism, and without relying on external devices.

公开(公告)号：US10725957B1

公开(公告)日：2020-07-28

申请号：US16460897

申请日：2019-07-02

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Thomas A. Volpe ,  Nafea Bshara ,  Yaniv Shapira ,  Adi Habusha

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16

Abstract: A plurality of system on chips (SoCs) in a server computer can be coupled to a plurality of memory agents (MAs) via respective Serializer/Deserializer (SerDes) interfaces. Each of the plurality of MAs can include one or more memory controllers to communicate with a memory coupled to the respective MA, and globally addressable by each of the SoCs. Each of the plurality of SoCs can access the memory coupled to any of the MAs in uniform number of hops using the respective SerDes interfaces. Different types of memories, e.g., volatile memory, persistent memory, can be supported.