公开(公告)号：US11411607B2

公开(公告)日：2022-08-09

申请号：US17137152

申请日：2020-12-29

Applicant: Analog Devices, Inc.

Inventor： Martin Kessler ,  Christopher M. Hanna ,  Eric M. Cline

IPC: H04B1/00 ,  H04B3/50 ,  H04B1/7136 ,  H04L25/49 ,  H04L27/00 ,  H05B47/18 ,  H05B45/325 ,  B60R16/023 ,  B60Q9/00 ,  H05B47/12 ,  H04R3/00

Abstract: Disclosed herein are systems and techniques for audio and lighting control in a bus system. For example, in some embodiments, a bus system may be configured for operation as a light organ and/or to generate sound effects based on accelerometer data.

公开(公告)号：US11874791B2

公开(公告)日：2024-01-16

申请号：US17589715

申请日：2022-01-31

Applicant: Analog Devices, Inc.

Inventor： Martin Kessler ,  Miguel A. Chavez ,  Lewis F. Lahr ,  William Hooper ,  Robert Adams ,  Peter Sealey

IPC: G06F13/42 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403 ,  G06F13/364 ,  H04R29/00

CPC classification number: G06F13/426 ,  G05B19/0421 ,  G05B19/0423 ,  G05B19/4185 ,  G06F1/26 ,  G06F1/266 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4291 ,  G06F13/4295 ,  H04B3/542 ,  H04B3/548 ,  H04L12/4035 ,  H04B2203/547 ,  H04R29/007 ,  Y02D10/00

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

公开(公告)号：US11409690B2

公开(公告)日：2022-08-09

申请号：US17110126

申请日：2020-12-02

Applicant: Analog Devices, Inc.

Inventor： Martin Kessler ,  Lewis F. Lahr ,  William Hooper

IPC: G06F13/42

Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

公开(公告)号：US10884972B2

公开(公告)日：2021-01-05

申请号：US16406329

申请日：2019-05-08

Applicant: Analog Devices, Inc.

Inventor： Martin Kessler ,  Lewis F. Lahr ,  William Hooper

IPC: G06F13/42

Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

公开(公告)号：US10649948B2

公开(公告)日：2020-05-12

申请号：US16427131

申请日：2019-05-30

Applicant: Analog Devices, Inc.

Inventor： Martin Kessler ,  Miguel Chavez ,  Lewis F. Lahr ,  William Hooper ,  Robert Adams ,  Peter Sealey

IPC: G06F13/42 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403 ,  G06F13/364 ,  H04R29/00

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

公开(公告)号：US09946680B2

公开(公告)日：2018-04-17

申请号：US14884987

申请日：2015-10-16

Applicant: ANALOG DEVICES, INC.

Inventor： Miguel Chavez ,  Martin Kessler

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/364 ,  G06F1/26 ,  G05B19/042 ,  G05B19/418 ,  H04B3/54 ,  H04L12/403 ,  H04R29/00

CPC classification number: G06F13/426 ,  G05B19/0421 ,  G05B19/0423 ,  G05B19/4185 ,  G06F1/26 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4291 ,  G06F13/4295 ,  H04B3/542 ,  H04B3/548 ,  H04B2203/547 ,  H04L12/4035 ,  H04R29/007 ,  Y02D10/14 ,  Y02D10/151

Abstract: Disclosed herein are systems and techniques for peripheral device diagnostics and control over a two-wire communication bus. For example, in some embodiments, a slave device may include circuitry to receive a synchronization control frame from an upstream device, receive audio data from the upstream device subsequent to receipt of the synchronization control frame, provide a synchronization response frame toward the upstream device, and provide first data representative of an operational characteristic of an audio device coupled to the slave device subsequent to provision of the synchronization response frame; circuitry to derive timing information from the synchronization control frame; and circuitry to provide the audio data to the audio device, and receive, from a sensor coupled to the slave device, second data representative of the operational characteristic of the audio device.

公开(公告)号：US09946679B2

公开(公告)日：2018-04-17

申请号：US14884947

申请日：2015-10-16

Applicant: ANALOG DEVICES, INC.

Inventor： Miguel Chavez ,  Martin Kessler

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/364 ,  G06F1/26 ,  G05B19/042 ,  G05B19/418 ,  H04B3/54 ,  H04L12/403 ,  H04R29/00

CPC classification number: G06F13/426 ,  G05B19/0421 ,  G05B19/0423 ,  G05B19/4185 ,  G06F1/26 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4291 ,  G06F13/4295 ,  H04B3/542 ,  H04B3/548 ,  H04B2203/547 ,  H04L12/4035 ,  H04R29/007 ,  Y02D10/14 ,  Y02D10/151

Abstract: Disclosed herein are systems and technique for distributed audio coordination over a two-wire communication bus. For example, in some embodiments, a first slave device may include circuitry to receive, over a two-wire bus a synchronization control frame, audio data, and a dynamics processor (DP) parameter for a second audio device coupled to a second slave device. The first slave device may include circuitry to derive timing information from the synchronization control frame, and circuitry to provide the audio data and a DP parameter (based on the DP parameter for the second audio device) to a first audio device coupled to the first slave device.

公开(公告)号：US10856199B2

公开(公告)日：2020-12-01

申请号：US16239798

申请日：2019-01-04

Applicant: Analog Devices, Inc.

Inventor： Martin Kessler

IPC: H04W36/30 ,  H04W36/08 ,  H04W4/90 ,  H04W84/20

Abstract: Disclosed herein are systems and techniques for auxiliary master and/or auxiliary call support functionality. For example, in some embodiments, a communication system with auxiliary master functionality may include a master node coupled to a plurality of downstream slave nodes, wherein at least one of the slave nodes may perform master node functions when the master node is disconnected from the system.

公开(公告)号：US10397021B2

公开(公告)日：2019-08-27

申请号：US15411706

申请日：2017-01-20

Applicant: Analog Devices, Inc.

Inventor： Martin Kessler ,  William Hooper ,  Lewis F. Lahr

IPC: G06F13/40 ,  G06F13/42 ,  H04L12/40 ,  H04L12/43

Abstract: Disclosed herein are systems and techniques for slave-to-slave communication in a multi-node, daisy-chained network. Slave nodes may provide or receive upstream or downstream data directly to/from other slave nodes, without the need for data slots first to route through the master node.

公开(公告)号：US10311010B2

公开(公告)日：2019-06-04

申请号：US14884900

申请日：2015-10-16

Applicant: ANALOG DEVICES, INC.

Inventor： Martin Kessler ,  Miguel Chavez ,  Lewis F. Lahr ,  William Hooper ,  Robert Adams ,  Peter Sealey

IPC: G06F13/42 ,  G06F13/364 ,  G06F1/26 ,  G05B19/042 ,  G05B19/418 ,  H04B3/54 ,  H04L12/403 ,  H04R29/00

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.