公开(公告)号：US09312840B2

公开(公告)日：2016-04-12

申请号：US14194107

申请日：2014-02-28

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yunzhi Dong ,  Zhao Li ,  Richard E. Schreier ,  Hajime Shibata ,  Trevor Clifford Caldwell

IPC: H03M1/38 ,  H03K5/159 ,  H03M1/14 ,  H03M1/06 ,  H03M3/00

CPC classification number: H03K5/159 ,  H03M1/0626 ,  H03M1/14 ,  H03M1/145 ,  H03M1/38 ,  H03M3/414 ,  H03M3/464

Abstract: This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.

Abstract translation: 本公开描述了使用被动连续时间（CT）延迟线用于高速CT模数转换器（ADC）应用的技术和方法。 在这些CT ADC通用的连续时间残留产生阶段，模拟输入和DAC输出之间的适当延迟至关重要。 具体来说，使用电感 - 电容（LC）晶格延迟元件来实现高性能CT流水线ADC和CT delta-sigma（＆Dgr＆amp; Sgr）ADC。 使用基于LC晶格的延迟元件为具有良好控制的阻抗的连续时间信号提供宽带群延迟。 这将是构建高性能CT ADC的重要电路元件，特别是在需要CT信号与其数字化版本之间产生低噪声和低失真残差的架构中。 基于LC晶格的延迟元件实现了高速连续时间流水线ADC和Δ-ΣADC所需的无噪声，无失真的宽带延迟。

公开(公告)号：US20150249445A1

公开(公告)日：2015-09-03

申请号：US14194107

申请日：2014-02-28

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yunzhi Dong ,  Zhao Li ,  Richard E. Schreier ,  Hajime Shibata ,  Trevor Clifford Caldwell

IPC: H03K5/159 ,  H03M1/38 ,  H03M3/00 ,  H03M1/06

CPC classification number: H03K5/159 ,  H03M1/0626 ,  H03M1/14 ,  H03M1/145 ,  H03M1/38 ,  H03M3/414 ,  H03M3/464

Abstract: This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.

Abstract translation: 本公开描述了使用被动连续时间（CT）延迟线用于高速CT模数转换器（ADC）应用的技术和方法。 在这些CT ADC通用的连续时间残留产生阶段，模拟输入和DAC输出之间的适当延迟至关重要。 具体来说，使用电感 - 电容（LC）晶格延迟元件来实现高性能CT流水线ADC和CT delta-sigma（＆Dgr＆amp; Sgr）ADC。 使用基于LC晶格的延迟元件为具有良好控制的阻抗的连续时间信号提供宽带群延迟。 这将是构建高性能CT ADC的重要电路元件，特别是在需要CT信号与其数字化版本之间产生低噪声和低失真残差的架构中。 基于LC晶格的延迟元件实现了高速连续时间流水线ADC和Δ-ΣADC所需的无噪声，无失真的宽带延迟。

公开(公告)号：US20150109158A1

公开(公告)日：2015-04-23

申请号：US14057153

申请日：2013-10-18

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yunzhi Dong ,  Hajime Shibata ,  Wenhua W. Yang ,  Richard E. Schreier

IPC: H03M3/00

CPC classification number: H03M3/344 ,  H03M1/00 ,  H03M1/12 ,  H03M1/144 ,  H03M1/145 ,  H03M3/30 ,  H03M3/416 ,  H04L25/067 ,  H04M1/72519

Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (ΔΣ) modulator is provided at the front-end of the MASH ADC, and another full ΔΣ modulator is provided at the back-end of the MASH ADC. The front-end ΔΣ modulator digitizes an analog input signal, and the back-end ΔΣ modulator digitizes an error between the output of the front-end ΔΣ modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.

Abstract translation: 本公开描述了一种用于将模拟输入信号转换为数字输出信号的改进的多级噪声整形（MASH）模数转换器（ADC）。 特别地，在MASH ADC的前端提供了一个完整的delta-sigma（＆Dgr＆amp; Sgr）调制器，另一个完整的＆Dgr＆amp; 调制器设置在MASH ADC的后端。 前端＆Dgr＆＆ 调制器将模拟输入信号数字化，后端＆Dgr＆amp; 调制器数字化前端＆Dgr＆amp; Sgr的输出之间的误差; 调制器和（原始）模拟输入信号。 在这种配置中，后端调制器将（全）前端调制器的误差数字化，前端的一些设计约束被放宽。 这些设计约束包括热噪声，数字噪声消除滤波器复杂度（前端的量化噪声已经由前端的噪声传递函数形成）和/或非线性。

公开(公告)号：US20150022386A1

公开(公告)日：2015-01-22

申请号：US13945647

申请日：2013-07-18

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Kevin Cao-Van Lam ,  Richard E. Schreier ,  Donald W. Paterson

IPC: H03M1/10

CPC classification number: H03M3/38 ,  H03M1/1009 ,  H03M3/392 ,  H03M3/424 ,  H03M3/454

Abstract: An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC. In a specific embodiment, the component calculator uses an algebraic function of a normalized representation of the application parameter to approximately evaluate at least one normalized ADC coefficient. The component value is further calculated by denormalizing the normalized ADC coefficient. In another specific embodiment, the component calculator uses an algebraic function of the application parameter to calculate the component value. In some embodiments, the integrated circuit further includes a scaling module configured to scale the component value based on scaling parameters.

Abstract translation: 集成电路包括：组件计算器，被配置为从至少一个应用参数计算高可编程模数转换器（ADC）的至少一个分量值;以及映射模块，被配置为将分量值映射到对应的寄存器设置 基于至少一个工艺参数，其中所述集成电路产生能够编程所述ADC的数字控制信号。 在具体实施例中，组件计算器使用应用参数的归一化表示的代数函数来近似评估至少一个归一化的ADC系数。 通过对归一化的ADC系数进行非归一化来进一步计算分量值。 在另一具体实施例中，组件计算器使用应用参数的代数函数来计算组件值。 在一些实施例中，集成电路还包括缩放模块，其被配置为基于缩放参数来缩放分量值。