公开(公告)号：US08884802B2

公开(公告)日：2014-11-11

申请号：US13920083

申请日：2013-06-18

Applicant: Analog Devices Technology

Inventor： Zhao Li ,  Shipra Bhal ,  Kevin Glenn Gard ,  David Alldred ,  Christopher Mayer ,  Trevor Clifford Caldwell ,  David J. McLaurin ,  Victor Kozlov

IPC: H03M1/34 ,  H03M1/10 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M3/384 ,  H03M1/00 ,  H03M1/1009 ,  H03M1/12 ,  H03M3/458

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract translation: 用于模数转换器（ADC）的校准系统，内部ADC接收模拟输入并将模拟输入转换为数字多位数据。 该校准系统还包括一个参考混洗电路，它洗牌内部ADC的比较器参考值。 此外，校准系统包括校准电路，校准内部ADC的比较器。 校准系统包括基于数字多位数据测量幅度的数字块。 此外，校准系统包括基于数字块的输出来控制校准电路的校准逻辑。

公开(公告)号：US09312840B2

公开(公告)日：2016-04-12

申请号：US14194107

申请日：2014-02-28

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yunzhi Dong ,  Zhao Li ,  Richard E. Schreier ,  Hajime Shibata ,  Trevor Clifford Caldwell

IPC: H03M1/38 ,  H03K5/159 ,  H03M1/14 ,  H03M1/06 ,  H03M3/00

CPC classification number: H03K5/159 ,  H03M1/0626 ,  H03M1/14 ,  H03M1/145 ,  H03M1/38 ,  H03M3/414 ,  H03M3/464

Abstract: This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.

Abstract translation: 本公开描述了使用被动连续时间（CT）延迟线用于高速CT模数转换器（ADC）应用的技术和方法。 在这些CT ADC通用的连续时间残留产生阶段，模拟输入和DAC输出之间的适当延迟至关重要。 具体来说，使用电感 - 电容（LC）晶格延迟元件来实现高性能CT流水线ADC和CT delta-sigma（＆Dgr＆amp; Sgr）ADC。 使用基于LC晶格的延迟元件为具有良好控制的阻抗的连续时间信号提供宽带群延迟。 这将是构建高性能CT ADC的重要电路元件，特别是在需要CT信号与其数字化版本之间产生低噪声和低失真残差的架构中。 基于LC晶格的延迟元件实现了高速连续时间流水线ADC和Δ-ΣADC所需的无噪声，无失真的宽带延迟。

公开(公告)号：US20150249445A1

公开(公告)日：2015-09-03

申请号：US14194107

申请日：2014-02-28

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yunzhi Dong ,  Zhao Li ,  Richard E. Schreier ,  Hajime Shibata ,  Trevor Clifford Caldwell

IPC: H03K5/159 ,  H03M1/38 ,  H03M3/00 ,  H03M1/06

CPC classification number: H03K5/159 ,  H03M1/0626 ,  H03M1/14 ,  H03M1/145 ,  H03M1/38 ,  H03M3/414 ,  H03M3/464

Abstract: This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.

Abstract translation: 本公开描述了使用被动连续时间（CT）延迟线用于高速CT模数转换器（ADC）应用的技术和方法。 在这些CT ADC通用的连续时间残留产生阶段，模拟输入和DAC输出之间的适当延迟至关重要。 具体来说，使用电感 - 电容（LC）晶格延迟元件来实现高性能CT流水线ADC和CT delta-sigma（＆Dgr＆amp; Sgr）ADC。 使用基于LC晶格的延迟元件为具有良好控制的阻抗的连续时间信号提供宽带群延迟。 这将是构建高性能CT ADC的重要电路元件，特别是在需要CT信号与其数字化版本之间产生低噪声和低失真残差的架构中。 基于LC晶格的延迟元件实现了高速连续时间流水线ADC和Δ-ΣADC所需的无噪声，无失真的宽带延迟。

公开(公告)号：US20140266825A1

公开(公告)日：2014-09-18

申请号：US13920083

申请日：2013-06-18

Applicant: Analog Devices Technology

Inventor： Zhao Li ,  Shipra Bhal ,  Kevin Glenn Gard ,  David Alldred ,  Christopher Mayer ,  Trevor Clifford Caldwell ,  David J. McLaurin ,  Victor Kozlov

IPC: H03M1/10

CPC classification number: H03M3/384 ,  H03M1/00 ,  H03M1/1009 ,  H03M1/12 ,  H03M3/458

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract translation: 用于模数转换器（ADC）的校准系统，内部ADC接收模拟输入并将模拟输入转换为数字多位数据。 该校准系统还包括一个参考混洗电路，它洗牌内部ADC的比较器参考值。 此外，校准系统包括校准电路，校准内部ADC的比较器。 校准系统包括基于数字多位数据测量幅度的数字块。 此外，校准系统包括基于数字块的输出来控制校准电路的校准逻辑。

公开(公告)号：US09148168B2

公开(公告)日：2015-09-29

申请号：US14065732

申请日：2013-10-29

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Zhao Li ,  David Alldred

IPC: H03M1/10 ,  H03M3/00 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M3/368 ,  H03M1/00 ,  H03M1/12 ,  H03M3/30 ,  H03M3/38 ,  H03M3/424 ,  H03M3/454

Abstract: An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.

Abstract translation: 模数转换器（ADC）可以包括连续时间ΔΣ调制器和校准逻辑。 校准逻辑可以校准连续时间Δ-Σ调制器的直接反馈和闪速时钟延迟系数，而不中断ADC的正常操作（例如，原位）。 因此，校准逻辑可以通过校准次优系数来纠正性能和稳定性降级。

公开(公告)号：US20150116138A1

公开(公告)日：2015-04-30

申请号：US14065732

申请日：2013-10-29

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Zhao Li ,  David Alldred

IPC: H03M3/00

CPC classification number: H03M3/368 ,  H03M1/00 ,  H03M1/12 ,  H03M3/30 ,  H03M3/38 ,  H03M3/424 ,  H03M3/454

Abstract: An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.

Abstract translation: 模数转换器（ADC）可以包括连续时间ΔΣ调制器和校准逻辑。 校准逻辑可以校准连续时间Δ-Σ调制器的直接反馈和闪速时钟延迟系数，而不中断ADC的正常操作（例如，原位）。 因此，校准逻辑可以通过校准次优系数来纠正性能和稳定性降级。