公开(公告)号：US20240321584A1

公开(公告)日：2024-09-26

申请号：US18603360

申请日：2024-03-13

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee ,  Benjamin Colombeau ,  Edy Cardona ,  Christopher S. Olsen ,  Shawn Thomas

IPC: H01L21/3065 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/3065 ,  H01L21/02057 ,  H01L21/02236 ,  H01L21/02532 ,  H01L29/66439

Abstract: Semiconductor devices, such as gate-all-around (GAA) devices, and methods of forming semiconductor devices are described. Selective oxidation processes that are useful in front-end of line (FEOL) and back-end of line (BEOL) applications and processes are also described. In FEOL processes, for example, selective oxidation protects silicon germanium (SiGe) layers during etching silicon (Si) channel recess when there is no dielectric inner spacer present. In BEOL processes, for example, selective oxidation protects growth of silicon germanium (SiGe) layers on the sidewall of a superlattice structure during bottom-up epitaxial growth.

公开(公告)号：US20230307506A1

公开(公告)日：2023-09-28

申请号：US18121718

申请日：2023-03-15

Applicant: Applied Materials, Inc.

Inventor： Nicolas Breil ,  Matthew Cogorno ,  Anchuan Wang ,  Byeong Chan Lee ,  Manoj Vellaikal

IPC: H01L29/40 ,  H01L21/3065 ,  C23C16/24 ,  C23C16/56 ,  C23C16/52

CPC classification number: H01L29/401 ,  H01L21/3065 ,  C23C16/24 ,  C23C16/56 ,  C23C16/52 ,  H01L29/45

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises non-selectively depositing an amorphous silicon layer on a top surface and a sidewall surface of at least one contact trench on a substrate and a crystalline silicon layer on a bottom surface of the at least one contact trench at a temperature less than or equal to 400° C., the bottom surface including a source/drain material. The amorphous silicon layer is selectively removed from the top surface and the sidewall surface at a temperature less than or equal to 400° C. The method may be performed in a processing chamber without breaking vacuum.

公开(公告)号：US20220399457A1

公开(公告)日：2022-12-15

申请号：US17888894

申请日：2022-08-16

Applicant: Applied Materials, Inc.

Inventor： Steven C.H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  C30B29/06 ,  C30B29/52 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/56 ,  C23C16/455

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US11450759B2

公开(公告)日：2022-09-20

申请号：US17037941

申请日：2020-09-30

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  C30B29/06 ,  C30B29/52 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/56 ,  C23C16/455

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US11189710B2

公开(公告)日：2021-11-30

申请号：US16874889

申请日：2020-05-15

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee ,  Tejinder Singh ,  Bencherki Mebarki

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/033 ,  H01L29/786

Abstract: Method of forming an electronic device with a bottom isolation dielectric between a pair of gate stacks is described. Each of the gate stacks comprises a plurality of gate layers. A sacrificial film having a liner on a top and side thereof is on top of the gate layers. A capping layer is on the top of the liner.

公开(公告)号：US20200373411A1

公开(公告)日：2020-11-26

申请号：US16874889

申请日：2020-05-15

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee ,  Tejinder Singh ,  Bencherki Mebarki

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/3105 ,  H01L29/423 ,  H01L21/02

Abstract: Method of forming an electronic device with a bottom isolation dielectric between a pair of gate stacks is described. Each of the gate stacks comprises a plurality of gate layers. A sacrificial film having a liner on a top and side thereof is on top of the gate layers. A capping layer is on the top of the liner.

公开(公告)号：US20200373168A1

公开(公告)日：2020-11-26

申请号：US16850265

申请日：2020-04-16

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/06

Abstract: A method may include forming a plasma of a fluorine-containing precursor and contacting a semiconductor substrate with plasma effluents. The semiconductor substrate may include a layer of a first silicon-containing material having a first germanium content formed over the semiconductor substrate, and alternating layers of a second silicon-containing material and a third silicon-containing material over the layer of the first silicon-containing material. The third silicon-containing material may have a second germanium content. The method may further include laterally recessing the third silicon-containing material relative to the first and second silicon-containing materials. The method may further include depositing a spacer material adjacent to the third silicon-containing material relative to the first and second silicon-containing materials. The method may also include etching the first silicon-containing material relative to the second silicon-containing material and the spacer material.