公开(公告)号：US11410885B2

公开(公告)日：2022-08-09

申请号：US16864623

申请日：2020-05-01

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522

Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.

公开(公告)号：US20220130676A1

公开(公告)日：2022-04-28

申请号：US17569870

申请日：2022-01-06

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik ,  Wenting Hou ,  Jianxin Lei ,  Chen Gong ,  Yong Cao

IPC: H01L21/285 ,  H01L21/768 ,  C23C14/56 ,  C23C14/14 ,  C23C14/24 ,  C23C14/06

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

公开(公告)号：US11257677B2

公开(公告)日：2022-02-22

申请号：US16751691

申请日：2020-01-24

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik ,  Wenting Hou ,  Jianxin Lei ,  Chen Gong ,  Yong Cao

IPC: C23C14/56 ,  H01L21/285 ,  H01L21/768 ,  C23C14/14 ,  C23C14/24 ,  C23C14/06

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

公开(公告)号：US11101174B2

公开(公告)日：2021-08-24

申请号：US16653601

申请日：2019-10-15

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  Nikolaos Bekiaris ,  Erica Chen ,  Mehul B. Naik

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/762 ,  H01L21/285 ,  H01L21/02 ,  H01L21/30 ,  H01L21/324 ,  H01L21/3213

Abstract: Methods for forming an interconnections structure on a substrate in a cluster processing system and thermal processing such interconnections structure are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a barrier layer in an opening formed in a material layer disposed on a substrate, forming an interface layer on the barrier layer, forming a gap filling layer on the interface layer, and performing an annealing process on the substrate, wherein the annealing process is performed at a pressure range greater than 5 bar.

公开(公告)号：US20210233770A1

公开(公告)日：2021-07-29

申请号：US16751691

申请日：2020-01-24

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik ,  Wenting Hou ,  Jianxin Lei ,  Chen Gong ,  Yong Cao

IPC: H01L21/285 ,  H01L21/768 ,  C23C14/06 ,  C23C14/14 ,  C23C14/24 ,  C23C14/56

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

公开(公告)号：US11830725B2

公开(公告)日：2023-11-28

申请号：US17153450

申请日：2021-01-20

Applicant: Applied Materials, Inc.

Inventor： Naomi Yoshida ,  He Ren ,  Hao Jiang ,  Chenfei Shen ,  Chi-Chou Lin ,  Hao Chen ,  Xuesong Lu ,  Mehul B. Naik

IPC: H01L21/02 ,  H01L21/28 ,  B08B5/02 ,  H01L29/66 ,  H01L21/3205

CPC classification number: H01L21/02057 ,  B08B5/02 ,  H01L21/28026 ,  H01L21/32051 ,  H01L29/66795

Abstract: Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.

公开(公告)号：US20230045689A1

公开(公告)日：2023-02-09

申请号：US17968201

申请日：2022-10-18

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  Chi Lu ,  He Ren ,  Chi-I Lang ,  Ho-yung David Hwang ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/027

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

公开(公告)号：US20210125864A1

公开(公告)日：2021-04-29

申请号：US16662200

申请日：2019-10-24

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  Chi Lu ,  He Ren ,  Chi-I Lang ,  Ho-yung David Hwang ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/203 ,  H01L21/306 ,  H01L21/3213

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

公开(公告)号：US10957533B2

公开(公告)日：2021-03-23

申请号：US16656018

申请日：2019-10-17

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  He Ren ,  Hao Chen ,  Mehul B. Naik

IPC: H01L21/02 ,  H01L21/30 ,  H01L21/477 ,  H01L21/3213 ,  H01L21/67

Abstract: Embodiments of the present disclosure provide methods and apparatus for forming and patterning features in a film stack disposed on a substrate. In one embodiment, a method for patterning a conductive layer on a substrate includes supplying a gas mixture comprising a chlorine containing gas at a first flow rate to etch a first conductive layer disposed on the substrate, lowing the chlorine containing gas in the first gas mixture to a second flow rate lower than the first flow rate to continue etching the first conductive layer, and increasing the chlorine containing gas in the first gas mixture to a third flow rate greater than the second flow rate to remove the first conductive layer from the substrate.

公开(公告)号：US20200350206A1

公开(公告)日：2020-11-05

申请号：US16864623

申请日：2020-05-01

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522

Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.