中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.008 seconds)

    BARRIER LAYER FOR PREVENTING ALUMINUM DIFFUSION
    1.
    发明公开
    BARRIER LAYER FOR PREVENTING ALUMINUM DIFFUSION 审中-公开

    公开(公告)号：US20230377879A1

    公开(公告)日：2023-11-23

    申请号：US17747978

    申请日：2022-05-18

    Applicant: Applied Materials, Inc.

    Inventor： Srinivas Gandikota ,  Elizabeth Mao ,  Tianyi Huang ,  Tengzhou Ma ,  Chi-Chou Lin ,  Yixiong Yang

    IPC: H01L21/02

    CPC classification number: H01L21/02362 ,  H01L21/02153 ,  H01L21/02181

    Abstract: Embodiments of the present disclosure are related to methods of preventing aluminum diffusion in a metal gate stack (e.g., high-κ metal gate (HKMG) stacks and nMOS FET metal gate stacks). Some embodiments relate to a barrier layer for preventing aluminum diffusion into high-κ metal oxide layers. The barrier layer described herein is configured to reduce threshold voltage (Vt) shift and reduce leakage in the metal gate stacks. Additional embodiments relate to methods of forming a metal gate stack having the barrier layer described herein. The barrier layer may include one or more of amorphous silicon (a-Si), titanium silicon nitride (TiSiN), tantalum nitride (TaN), or titanium tantalum nitride (TiTaN).

    INTEGRATED DIPOLE REGION FOR TRANSISTOR
    4.
    发明公开
    INTEGRATED DIPOLE REGION FOR TRANSISTOR 审中-公开

    公开(公告)号：US20240332008A1

    公开(公告)日：2024-10-03

    申请号：US18126583

    申请日：2023-03-27

    Applicant: Applied Materials, Inc.

    Inventor： Geetika Bajaj ,  Tianyi Huang ,  Hsin-Jung Yu ,  Yixiong Yang ,  Srinivas Gandikota ,  Chi-Chou Lin ,  Pei Hsuan Lin

    IPC: H01L21/02 ,  H01L21/28

    CPC classification number: H01L21/02321 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/28229

    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-κ dielectric layer on the interfacial layer, a dipole layer on the high-κ dielectric layer, and a capping layer on the dipole layer. In some embodiments, the dipole layer comprises a metal oxynitride (MON), such as aluminum oxynitride (AlON). In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-κ dielectric layer.

    MULTI-PULSE DEPOSITION PROCESSES
    5.
    发明公开
    MULTI-PULSE DEPOSITION PROCESSES 审中-公开

    公开(公告)号：US20240183033A1

    公开(公告)日：2024-06-06

    申请号：US18074197

    申请日：2022-12-02

    Applicant: Applied Materials, Inc.

    Inventor： Tianyi Huang ,  Srinivas Gandikota ,  Yixiong Yang ,  Elizabeth Mao ,  Chi-Chou Lin

    IPC: C23C16/455 ,  C23C16/34 ,  H01L21/3205 ,  H01L21/768

    CPC classification number: C23C16/45527 ,  C23C16/34 ,  H01L21/32051 ,  H01L21/76843

    Abstract: Embodiments of the present disclosure advantageously provide improved control over precursor/reactant pulse/purge time, greater growth per cycle, and higher throughput during formation of a metal-containing film on a substrate surface (including substrate surfaces having at least one feature) compared to traditional atomic layer deposition (ALD) processes. In some embodiments, forming the metal-containing film comprises exposing a substrate to a constant flow of an inert carrier gas and a co-flow of a pulse of a metal-containing precursor and a pulse of a reactant. The pulse of the metal-containing precursor and the pulse of the reactant may be interrupted by a mini purge. The metal-containing precursor and/or the reactant may be charged during the mini purge to avoid precursor/reactant depletion.

Patent Agency Ranking