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公开(公告)号：US10776120B2
公开(公告)日：2020-09-15
申请号：US15555239
申请日：2016-02-11
Applicant: ARM LIMITED
Inventor： Michael John Williams , John Michael Horley , Stephan Diestelhorst , Richard Roy Grisenthwaite
Abstract: There is provided an apparatus comprising processing circuitry to execute a transaction comprising a number of program instructions that execute to generate updates to state data, to commit the updates if the transaction completes without a conflict, and to generate trace control signals during execution of the number of program instructions. The processing circuitry uses at least one resource during execution of the program instructions. Transaction trace circuitry generates trace items in response to the trace control signals. In response to the trace control signals indicating that a change in a usage level of the at least one resource has occurred during execution of the program instructions, the transaction trace circuitry generates at least one trace item that indicates the usage level of the at least one resource.
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公开(公告)号：US09229908B2
公开(公告)日：2016-01-05
申请号：US13934741
申请日：2013-07-03
Applicant: ARM Limited
Inventor： John Michael Horley , Andrew Brookfield Swaine , Michael John Williams
Abstract: A data processing apparatus is provided which is configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M≦N. The data processing apparatus comprises a selection storage unit configured to store at least N+1 identifier selection bits, wherein a position of a first marker bit in the at least N+1 identifier selection bits determines M, and an identifier selection unit configured to determine the 2M selected identifiers. The 2M selected identifiers fall within a range defined by a base identifier and a ceiling identifier. N-M bits of the N+1 identifier selection bits form N-M bits of the base identifier, and M zeroes form a further M bits of the base identifier. The ceiling identifier corresponds to the base identifier, except that the M zeroes of the base identifier are replaced by M ones.
Abstract translation: 提供了一种数据处理装置，其被配置为在最多2N个标识符的可能范围内选择2M个选择的标识符，其中M＆N; E; N。 数据处理装置包括：选择存储单元，被配置为存储至少N + 1个标识符选择位，其中，所述至少N + 1个标识符选择位中的第一标记位的位置确定M;以及标识符选择单元， 2M选择的标识符。 2M个选择的标识符落在由基本标识符和上限标识符定义的范围内。 N + 1标识符选择位的N-M位形成基本标识符的N-M位，并且M个零构成基本标识符的另外M位。 天花板标识符对应于基本标识符，除了基本标识符的M个零被M 1替换。
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公开(公告)号：US20140019501A1
公开(公告)日：2014-01-16
申请号：US13934741
申请日：2013-07-03
Applicant: ARM Limited
Inventor： John Michael HORLEY , Andrew Brookfield Swaine , Michael John Williams
IPC: G06F17/10
Abstract: A data processing apparatus is provided which is configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M≦N. The data processing apparatus comprises a selection storage unit configured to store at least N+1 identifier selection bits, wherein a position of a first marker bit in the at least N+1 identifier selection bits determines M, and an identifier selection unit configured to determine the 2M selected identifiers. The 2M selected identifiers fall within a range defined by a base identifier and a ceiling identifier. N-M bits of the N+1 identifier selection bits form N-M bits of the base identifier, and M zeroes form a further M bits of the base identifier. The ceiling identifier corresponds to the base identifier, except that the M zeroes of the base identifier are replaced by M ones.
Abstract translation: 提供了一种数据处理装置，其被配置为在最多2N个标识符的可能范围内选择2M个选择的标识符，其中M @ N。 数据处理装置包括：选择存储单元，被配置为存储至少N + 1个标识符选择位，其中，所述至少N + 1个标识符选择位中的第一标记位的位置确定M;以及标识符选择单元， 2M选择的标识符。 2M个选择的标识符落在由基本标识符和上限标识符定义的范围内。 N + 1标识符选择位的N-M位形成基本标识符的N-M位，并且M个零构成基本标识符的另外M位。 天花板标识符对应于基本标识符，除了基本标识符的M个零被M 1替换。
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公开(公告)号：US11354126B2
公开(公告)日：2022-06-07
申请号：US16975486
申请日：2019-02-15
Applicant: Arm Limited
Inventor： Michael John Williams , Nigel John Stephens
IPC: G06F9/30
Abstract: Data processing apparatus comprises vector processing circuitry to selectively apply vector processing operations defined by vector processing instructions to generate one or more data elements of a data vector comprising a plurality of data elements at respective data element positions of the data vector, according to the state of respective predicate flags associated with the positions of the data vector; and generator circuitry to generate instruction sample data indicative of processing activities of the vector processing circuitry for selected ones of the vector processing instructions, instruction sample data indicating at least the state of the predicate flags at execution of the selected vector processing instructions.
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公开(公告)号：US11194693B2
公开(公告)日：2021-12-07
申请号：US15711028
申请日：2017-09-21
Applicant: ARM LIMITED
Inventor： Anitha Kona , Michael John Williams , John Michael Horley , Alasdair Grant
IPC: G06F11/34
Abstract: A data processing apparatus is provided that includes monitor circuitry to produce local trace data indicating behaviour of the data processing apparatus. Interface circuitry communicates with a second data processing apparatus and encoding circuitry produces an encoded instruction to cause the local trace data to be stored in storage circuitry of the second data processing apparatus or to be output at output circuitry of the second data processing apparatus. The interface circuitry transmits the encoded instruction to the second data processing apparatus.
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Patent Agency Ranking
公开(公告)号：US20190171511A1
公开(公告)日：2019-06-06
申请号：US15830380
申请日：2017-12-04
Applicant: Arm Limited
Inventor： Anitha KONA , Michael John Williams , John Michael Horley , Alasdair Grant
Abstract: An apparatus includes processor circuitry to perform data processing operations. Interface circuitry forms a connection to a plurality of other apparatuses and receives a foreign exception message indicative of a foreign exception event having been triggered on one of the other apparatuses. In response to receiving the foreign exception message, the interface circuitry forwards the foreign exception message to a set of the plurality of other apparatuses.
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公开(公告)号：US10140216B2
公开(公告)日：2018-11-27
申请号：US15002648
申请日：2016-01-21
Applicant: ARM LIMITED
Inventor： Michael John Williams , Michael Filippo , Hazim Shafi
IPC: G06F12/10 , G06F12/1027 , G06F3/06 , G06F12/1009 , G06F11/34
Abstract: An apparatus includes processing circuitry to process instructions, some of which may require addresses to be translated. The apparatus also includes address translation circuitry to translate addresses in response to instruction processed by the processing circuitry. Furthermore, the apparatus also includes translation latency measuring circuitry to measure a latency of at least part of an address translation process performed by the address translation circuitry in response to a given instruction.
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公开(公告)号：US09201749B2
公开(公告)日：2015-12-01
申请号：US14448038
申请日：2014-07-31
Applicant: ARM Limited
Inventor： Michael John Williams , Richard Roy Grisenthwaite
CPC classification number: G06F11/2236 , G06F11/3632
Abstract: A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception.
Abstract translation: 一种用于控制处理器以单步模式执行使得来自指令流的单个指令被执行的方法和装置，处理器确定单个指令是否是至少一种预定类型的指令中的一种，并将类型指示器存储在 在处理器处理单个指令之后，采集数据存储位置和诊断异常。 此外，执行诊断操作，包括访问存储在数据存储位置中的类型指示符，并且当单个指令不是预定类型中的一个时，控制处理器以单步模式继续执行指令，并且当单个指令 指令是至少一种预定类型之一，控制处理器退出单步模式，并且不执行指令流内的下一条指令作为跟随异常的单个指令。
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公开(公告)号：US12204906B2
公开(公告)日：2025-01-21
申请号：US17999167
申请日：2021-05-20
Applicant: Arm Limited
Inventor： Michael John Williams , Alasdair Grant , John Michael Horley
Abstract: Processing circuitry performs data processing operations in response to instructions fetched from a cache or memory or micro-operations decoded from the instructions. Sampling circuitry selects a subset of instructions or micro-operations as sampled operations to be profiled. Profiling circuitry captures, in response to processing of an instruction or micro-operation selected as a sampled operation, a sample record specifying an operation type of the sampled operation and information about behaviour of the sampled operation which is directly attributed to the sampled operation. The profiling circuitry can include, in the sample record for a sampled operation corresponding to a given instruction, a reference instruction address indicator indicative of an address of a reference instruction appearing earlier or later in program order than the given instruction, for which control flow is sequential between any instructions occurring between the reference instruction and the given instruction in program order.
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公开(公告)号：US12045154B2
公开(公告)日：2024-07-23
申请号：US17998299
申请日：2021-05-13
Applicant: Arm Limited
Inventor： John Michael Horley , Michael John Williams , Mark Salling Rutland , Alasdair Grant
CPC classification number: G06F11/3466 , G06F9/3867 , G06F11/34 , G06F11/3636 , G06F9/3861 , G06F9/3865 , G06F2201/86 , G06F2201/865
Abstract: A technique for collecting state information of an apparatus comprising a processing pipeline for executing a sequence of instructions, and interesting instruction designation circuitry for identifying at least one of the instructions in the sequence as being an interesting instruction. Each interesting instruction is an instruction for which given state information of the apparatus associated with execution of that interesting instruction is to be collected. The interesting instruction designation circuitry is arranged, for each identified interesting instruction, to apply defined selection criteria to determine a further instruction later in the sequence of instructions than the interesting instruction, and to mark that further instruction as having a synchronous exception associated therewith. The processing pipeline is responsive to the further instruction, which causes the processing pipeline to execute a given exception handling routine in order to collect the given state information.
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