公开(公告)号：US11194577B2

公开(公告)日：2021-12-07

申请号：US15571915

申请日：2016-04-11

Applicant: Arm Limited

Inventor： Antony John Penton ,  Simon John Craske ,  Vladimir Vasekin

IPC: G06F9/30 ,  G06F9/38

Abstract: Apparatus for processing data (2) includes issue circuitry (22) for issuing program instructions (processing operations) to execute either within real time execution circuitry (32) or non real time execution circuitry (24, 26, 28, 30). Registers within a register file (18) are marked as non real time dependent registers if they are allocated to store a data value which is to be written by an uncompleted program instruction issued to the non real time execution circuitry and not yet completed. Issue policy control circuitry (42) responds to a trigger event to enter a real time issue policy mode to control the issue circuitry (22) to issue candidate processing operations (such as program instruction, micro-operations, architecturally triggered processing operations etc.) to one of the non real time execution circuitry or the real time execution circuitry in dependence upon whether that candidate processing operation reads a register marked as a non real time dependent register.

公开(公告)号：US10885313B2

公开(公告)日：2021-01-05

申请号：US16213814

申请日：2018-12-07

Applicant: Apical Ltd ,  Arm Limited

Inventor： Daren Croxford ,  Simon John Craske

IPC: G06K9/00 ,  G06F3/01 ,  G06K9/46 ,  G02B5/30 ,  G06N3/02 ,  G09G3/22 ,  G06K9/62

Abstract: Examples of the present disclosure relate to methods for controlling a display device. In one such example, data representing a result of an eyewear detection operation is obtained. Dependent on the obtained data, a control signal is outputted to adjust a display parameter of the display device. Performing the eyewear detection operation comprises receiving image data representing a user of the display device, and processing the image data using object recognition to determine whether or not the user is wearing eyewear of a predetermined type.

公开(公告)号：US10691701B2

公开(公告)日：2020-06-23

申请号：US15678430

申请日：2017-08-16

Applicant: ARM LIMITED

Inventor： Simon John Craske

IPC: G06F16/2457 ,  G06F16/22 ,  G06F7/22 ,  G06F7/00

Abstract: An apparatus comprises: selection circuitry to select the two most preferred items from a set of items having ranking information indicative of an order of preference for the set of items. The selection circuitry comprises at least one selection node circuit, each selection node circuit to receive as inputs an indication of a first pair of items and a second pair of items among the set of items, and comprises first selection circuitry and second selection circuitry. The first selection circuitry to first selection circuitry to select as a first selected item a most preferred one of: a most preferred ranked item of the first pair, and a least preferred item of the second pair. The second selection circuitry to select as a second selected item a most preferred one of: a least preferred item of the first pair, and a most preferred item of the second pair.

公开(公告)号：US10402203B2

公开(公告)日：2019-09-03

申请号：US15578477

申请日：2016-03-31

Applicant: ARM LIMITED

Inventor： Max John Batley ,  Simon John Craske ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus comprises prediction circuitry (40, 100, 80) for determining, based on current prediction policy information (43, 82, 104), a predicted behavior to be used for processing instructions. The current prediction policy information is updated based on an outcome of processing of instructions. A storage structure (50) stores at least one entry identifying previous prediction policy information (60) for a corresponding block of instructions. In response to an instruction from a block having a corresponding entry in the storage structure (50) which identifies the previous prediction policy information (60), the current prediction policy information (43, 82, 104) can be reset based on the previous prediction policy information 60 identified in the corresponding entry of the storage structure (50).

公开(公告)号：US10394641B2

公开(公告)日：2019-08-27

申请号：US15483155

申请日：2017-04-10

Applicant: ARM LIMITED

Inventor： Simon John Craske

IPC: G06F11/00 ,  G06F11/07

Abstract: An apparatus and method are described for handling memory access operations, and in particular for handling faults occurring during the processing of such memory access operations. The apparatus has processing circuitry for executing program instructions that include memory access instructions, and a memory interface for coupling the processing circuitry to a memory system. The processing circuitry is switchable between a synchronous fault handling mode and an asynchronous fault handling mode. When in the synchronous fault handling mode the processing circuitry applies a constraint on execution of the program instructions such that a fault resulting from a memory access operation processed by the memory system will be received by the memory interface before the processing circuitry has allowed program execution to proceed beyond a recovery point for the memory access instruction associated with the memory access operation. In contrast, when in the asynchronous fault handling mode, the processing circuitry removes that constraint. The processing circuitry is then arranged to switch between the synchronous fault handling mode and the asynchronous fault handling mode during execution of the program instructions, in dependence on a current context of the processing circuitry. This enables the apparatus to selectively take advantage of the higher performance associated with asynchronous reporting of faults, and the improved fault handling associated with the synchronous reporting of faults.

公开(公告)号：US10379989B2

公开(公告)日：2019-08-13

申请号：US13968991

申请日：2013-08-16

Applicant: ARM Limited

Inventor： John Michael Horley ,  Simon John Craske ,  Michael John Gibbs ,  Paul Anthony Gilkerson

IPC: G06F9/30 ,  G06F11/34

Abstract: A processing circuit is responsive to at least one conditional instruction to perform a conditional operation in dependence on a current value of a subset of at least one condition flag. A trace circuit is provided for generating trace data elements indicative of operations performed by the processing circuit. When the processing circuit 4 processes at least one selected instruction, then the trace circuit generates a trace data element including a traced condition value indicating at least the subset of condition flags required to determine the outcome of the conditional instruction. A corresponding diagnostic apparatus uses the traced condition value to determine a processing outcome of the at least one conditional instruction.

公开(公告)号：US10354092B2

公开(公告)日：2019-07-16

申请号：US14912300

申请日：2014-07-15

Applicant: ARM LIMITED

Inventor： Simon John Craske ,  Antony John Penton

IPC: G06F21/62 ,  G06F21/60 ,  G06F21/50 ,  G06F9/30 ,  G06F9/48 ,  G06F9/455 ,  G06F13/24 ,  G06F21/00 ,  G06F9/46

Abstract: A data processing apparatus (2) has processing circuitry (4) for executing first software (12) at a first privilege level EL1 and second software (10) at a second privilege level EL2 higher than the first privilege level. Attributes may be set by the first and second software (10, 12) to indicate whether execution of the data access instruction can be interrupted. For a predetermined type of data access instruction for which the second attribute set by the second software (10) specifies that the instruction can be interrupted, the instruction may be set as interruptable even if the first attribute set by the first software (12) specifies that the execution of the instruction cannot be interrupted.

公开(公告)号：US09983872B2

公开(公告)日：2018-05-29

申请号：US15666978

申请日：2017-08-02

Applicant: ARM Limited

Inventor： Simon John Craske ,  Richard Roy Grisenthwaite ,  Nigel John Stephens

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30003 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3842

Abstract: An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. A data processor is responsive to the decoded conditional select instruction and the condition (i) having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register, and (ii) not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

公开(公告)号：US09952871B2

公开(公告)日：2018-04-24

申请号：US14731789

申请日：2015-06-05

Applicant: ARM LIMITED

Inventor： Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Simon John Craske ,  Max John Batley ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3855 ,  G06F9/3873 ,  G06F9/3889

Abstract: An apparatus comprises a processing pipeline comprising out-of-order execution circuitry and second execution circuitry. Control circuitry monitors at least one reordering metric indicative of an extent to which instructions are executed out of order by the out-of-order execution circuitry, and controls whether instructions are executed using the out-of-order execution circuitry or the second execution circuitry based on the reordering metric. A speculation metric indicative of a fraction of executed instructions that are flushed due to a mis-speculation can also be used to determine whether to execute instructions on first or second execution circuitry having different performance or energy consumption characteristics.

公开(公告)号：US09940268B2

公开(公告)日：2018-04-10

申请号：US14762976

申请日：2013-02-05

Applicant: ARM LIMITED

Inventor： Simon John Craske ,  Richard Roy Grisenthwaite

IPC: G06F12/14 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1458 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1416 ,  G06F12/1441 ,  G06F12/145 ,  G06F12/1475 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/651

Abstract: A processing apparatus has a memory protection unit (MPU) 38 and an address translation unit (ATU) 120 which operate concurrently for memory access operations performed by processing circuitry 22. The MPU 38 stores access permission data for corresponding regions of an address space. The ATU 120 stores address translation entries for defining virtual-to-physical mappings for corresponding pages of the address space. In response to a memory access operation specifying a target address, one of the MPU 38 and the ATU 120 is selected to handle the memory access operation based on the target address. If the MPU 38 is selected then the target address is a physical address and the MPU 38 checks access permissions using a corresponding set of permission data. If the ATU 120 is selected then the target address is a virtual address and is translated into a physical address using a corresponding translation entry.