公开(公告)号：US11043262B2

公开(公告)日：2021-06-22

申请号：US15886630

申请日：2018-02-01

Applicant: Arm Limited

Inventor： Arjunesh Namboothiri Madhavan ,  Akash Bangalore Srinivasa ,  Sujit Kumar Rout ,  Vikash ,  Gaurav Rattan Singla ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Lalit Gupta

IPC: G11C11/419 ,  H01L29/94 ,  H01L27/11 ,  G11C7/10 ,  G11C7/18 ,  G11C8/16 ,  G11C7/12

Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

公开(公告)号：US10861575B2

公开(公告)日：2020-12-08

申请号：US16666164

申请日：2019-10-28

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Renu Rawat ,  Paul Darren Hoxey ,  Vikash ,  Kumaraswamy Ramanathan ,  Sanjay Mangal ,  Yew Keong Chong

IPC: G11C29/12 ,  G11C11/418 ,  G11C11/419 ,  G11C7/10 ,  G11C29/32 ,  G11C5/06

Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

公开(公告)号：US20190325962A1

公开(公告)日：2019-10-24

申请号：US15959048

申请日：2018-04-20

Applicant: Arm Limited

Inventor： Mohammed Saif Kunjatur Sheikh ,  Vikash ,  Andy Wangkun Chen

IPC: G11C15/04 ,  G06F11/10 ,  G11C29/42

Abstract: Various implementations described herein are directed to an integrated circuit having an array of bitcells. The integrated circuit may include latch circuitry having a latch for each row of bitcells that latches valid match data into the latch for each row of bitcells. The integrated circuit may include priority encoding circuitry that receives the valid match data from the latch for each row of bitcells. The integrated circuit may include first logic circuitry coupled between the array of bitcells and the priority encoding circuitry to assist with providing the valid match data to the latch circuitry.

公开(公告)号：US09583209B1

公开(公告)日：2017-02-28

申请号：US14963111

申请日：2015-12-08

Applicant: ARM Limited

Inventor： Rajiv Kumar Roy ,  Fakhruddin Ali Bohra ,  Manish Trivedi ,  Sumant Kumar Thapliyal ,  Vikash

IPC: G11C8/00 ,  G11C17/08

CPC classification number: G11C17/08 ,  G11C8/12

Abstract: Various implementations described herein are directed to an integrated circuit having high density memory architecture. The integrated circuit may include a plurality of bank arrays having multiple segments of bitcells configured to share local control. The integrated circuit may include a plurality of control lines coupling the local control to each of the multiple segments of bitcells. In some instances, during activation of a segment of bitcells by the local control via one of the control lines, another segment of bitcells may be deactivated by the local control via another of the control lines.

Abstract translation: 本文描述的各种实现涉及具有高密度存储器架构的集成电路。 集成电路可以包括具有被配置为共享本地控制的多个位单元段的多个存储体阵列。 集成电路可以包括将本地控制耦合到位单元的多个段中的每一个的多个控制线。 在一些情况下，在本地控制通过控制线之一激活位单元的段时，可以通过另一控制线的本地控制来停用另一段位单元。

公开(公告)号：US20160293247A1

公开(公告)日：2016-10-06

申请号：US14675687

申请日：2015-03-31

Applicant: ARM Limited

Inventor： Rejeesh Ammanath Vijayan ,  Vikash ,  Pradeep Raj ,  Neelima Gudipati ,  Manish Trivedi ,  Sujit Rout

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16

Abstract: Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.

Abstract translation: 本文描述的各种实现涉及用于读写争用的集成电路。 集成电路可以包括具有被配置为接收对应于每个端口的数据信号的多个端口的存储器电路。 集成电路可以包括争用覆盖电路，其基于检测端口之间的读写争用，为每个端口提供争用覆盖信号。 集成电路可以包括具有用于每个端口的多个通行口的写入电路，包括用于每个端口的写通行证和争用通行证。 写入通道可以用来自相应端口的数据信号输入。 可以基于相对的争用覆盖信号，从相对端口输入具有数据信号的争用通行证。