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公开(公告)号：US20210028995A1
公开(公告)日：2021-01-28
申请号：US16993678
申请日：2020-08-14
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, JR. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
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公开(公告)号：US10749756B2
公开(公告)日：2020-08-18
申请号：US15192287
申请日：2016-06-24
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, Jr. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
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公开(公告)号：US10103837B2
公开(公告)日：2018-10-16
申请号：US15191322
申请日：2016-06-23
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, Jr. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
Abstract: Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of ‘N’ clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines.
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公开(公告)号：US11860685B2
公开(公告)日：2024-01-02
申请号：US17514723
申请日：2021-10-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Luke Jereme Whitaker , Edoardo Prete
IPC: G06F1/28 , G06F1/08 , H03K17/693 , H03K23/00
CPC classification number: G06F1/08 , H03K17/693 , H03K23/00
Abstract: A system and method for efficiently generating clock signals are described. In various implementations, an integrated circuit includes multiple clock frequency dividers both at its I/O boundaries and across its die. A clock frequency divider utilizes a first clock divider and a second clock divider that receive input clock signals with an initial phase difference between them. The first clock divider and the second clock divider generate output clock signals that have frequencies that are a fraction of the frequencies of the received input clock signals. The second clock divider uses a combined multiplexer and flip-flop (combined mux-flop) circuit. The combined mux-flop circuit receives a reset signal that is asserted asynchronously with respect to an input clock signal received by the second clock divider. The second clock divider generates an output clock signal that has the initial phase difference with an output clock signal of the first clock divider.
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公开(公告)号：US20230308132A1
公开(公告)日：2023-09-28
申请号：US17705022
申请日：2022-03-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Dean E. Gonzales , Edoardo Prete , Milam Paraschou , Mark Chirachanchai , Gerald R. Talbot
Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. In order to better handle noise issues when using single-ended signaling, one or more of the receivers include equalization circuitry and termination circuitry. The termination circuitry prevents reflection on a corresponding transmission line ending at a corresponding receiver. The equalization circuitry uses a bridged T-coil circuit to provide continuous time linear equalization (CTLE) with no feedback loop. The equalization circuitry performs equalization by providing a high-pass filter that offsets the low-pass characteristics of a corresponding transmission line. A comparator of the receiver receives the input signal and compares it to a reference voltage. The placement of the comparator and the ratio of the inductances of the inductors of the bridged T-coil circuit are based on whether the receiver includes self-diagnostic circuitry.
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Patent Agency Ranking
公开(公告)号：US20230134926A1
公开(公告)日：2023-05-04
申请号：US17566199
申请日：2021-12-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Rajesh Kumar , Edoardo Prete , Gerald R. Talbot , Ethan Crain , Tracy J. Feist , Jeffrey Cooper
IPC: H03K19/0175 , H03F3/45
Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.
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公开(公告)号：US10692545B2
公开(公告)日：2020-06-23
申请号：US16140356
申请日：2018-09-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Milam Paraschou , Balwinder Singh , Gerald R. Talbot , Alushulla Jack Ambundo , Edoardo Prete , Thomas H. Likens, III , Michael A. Margules
IPC: G11C7/10 , G11C5/14 , G11C11/4074 , H04L25/02 , H03K17/687
Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.
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公开(公告)号：US20200098399A1
公开(公告)日：2020-03-26
申请号：US16140356
申请日：2018-09-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Milam Paraschou , Balwinder Singh , Gerald R. Talbot , Alushulla Jack Ambundo , Edoardo Prete , Thomas H. Likens, III , Michael A. Margules
IPC: G11C5/14 , H03K17/687 , H04L25/02 , G11C11/4074
Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.
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公开(公告)号：US20170373944A1
公开(公告)日：2017-12-28
申请号：US15192287
申请日：2016-06-24
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, JR. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
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公开(公告)号：US20170373788A1
公开(公告)日：2017-12-28
申请号：US15191322
申请日：2016-06-23
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, JR. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
CPC classification number: H04L1/0002 , H04L1/0073 , H04L1/244 , H04L7/0037 , H04L7/043 , H04L7/10 , H04L25/14 , H04L2012/5681
Abstract: Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of ‘N’ clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines.
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