公开(公告)号：US11443051B2

公开(公告)日：2022-09-13

申请号：US16228349

申请日：2018-12-20

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： Benjamin Koon Pan Chan ,  William Lloyd Atkinson ,  Tung Chuen Kwong ,  Guhan Krishnan

IPC: G06F21/62 ,  G06V10/94

Abstract: A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.

公开(公告)号：US20220100567A1

公开(公告)日：2022-03-31

申请号：US17120215

申请日：2020-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Guhan Krishnan

IPC: G06F9/50 ,  G06F13/16 ,  G06T1/60

Abstract: An electronic device includes a memory; a plurality of clients; at least one arbiter circuit; and a management circuit. A given client of the plurality of clients communicates a request to the management circuit requesting an allocation of memory access bandwidth for accesses of the memory by the given client. The management circuit then determines, based on the request, a set of memory access bandwidths including a respective memory access bandwidth for each of the given client and other clients of the plurality of clients that are allocated memory access bandwidth. The management circuit next configures the at least one arbiter circuit to use respective memory access bandwidths from the set of memory access bandwidths for the given client and the other clients for subsequent accesses of the memory.

公开(公告)号：US12045362B2

公开(公告)日：2024-07-23

申请号：US17889956

申请日：2022-08-17

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： Benjamin Koon Pan Chan ,  William Lloyd Atkinson ,  Tung Chuen Kwong ,  Guhan Krishnan

IPC: G06F21/62 ,  G06V10/94

CPC classification number: G06F21/6218 ,  G06V10/955

Abstract: A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.

公开(公告)号：US11449346B2

公开(公告)日：2022-09-20

申请号：US16718656

申请日：2019-12-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Jyoti Raheja ,  Hideki Kanayama ,  Guhan Krishnan ,  Ruihua Peng

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F12/0804 ,  G06F9/4401

Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.

公开(公告)号：US10572183B2

公开(公告)日：2020-02-25

申请号：US15787459

申请日：2017-10-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Sonu Arora ,  Guhan Krishnan ,  Kevin Brandl

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06

Abstract: A data processing system includes a memory and a data processor. The data processor is connected to the memory and adapted to access the memory in response to scheduled memory access requests. The data processor has power management logic that, in response to detecting a memory power state change, determines whether to retrain or suppress retraining of at least one parameter related to accessing the memory based on an operating state of the memory. The power management logic further determines a retraining interval for retraining the at least one parameter related to accessing the memory, and initiates a retraining operation in response to the memory power state change based on the operating state of the memory being outside of a predetermined threshold.

公开(公告)号：US20190114109A1

公开(公告)日：2019-04-18

申请号：US15787459

申请日：2017-10-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Sonu Arora ,  Guhan Krishnan ,  Kevin Brandl

IPC: G06F3/06

Abstract: A data processing system includes a memory and a data processor. The data processor is connected to the memory and adapted to access the memory in response to scheduled memory access requests. The data processor has power management logic that, in response to detecting a memory power state change, determines whether to retrain or suppress retraining of at least one parameter related to accessing the memory based on an operating state of the memory. The power management logic further determines a retraining interval for retraining the at least one parameter related to accessing the memory, and initiates a retraining operation in response to the memory power state change based on the operating state of the memory being outside of a predetermined threshold.

公开(公告)号：US20150277521A1

公开(公告)日：2015-10-01

申请号：US14225244

申请日：2014-03-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ashish Jain ,  Alexander J. Branover ,  Guhan Krishnan

IPC: G06F1/26

CPC classification number: G06F1/3225 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126

Abstract: A system has a plurality of electronic components including a memory, a PHY coupled to the memory, and one or more other electronic components. Power consumed by the PHY is estimated during operation of the system. Estimating the power consumed by the PHY includes modeling the power consumed by the PHY as a linear function with respect to memory bandwidth. Available power for the PHY is determined based at least in part on the estimated power consumed by the PHY. At least a portion of the available power for the PHY is allocated to at least one of the one or more other components.

Abstract translation: 系统具有包括存储器，耦合到存储器的PHY和一个或多个其它电子部件的多个电子部件。 在系统运行期间估计PHY消耗的功率。 估计PHY消耗的功率包括将PHY消耗的功率建模为相对于存储器带宽的线性函数。 至少部分地基于PHY消耗的估计功率来确定PHY的可用功率。 用于PHY的可用功率的至少一部分被分配给一个或多个其它组件中的至少一个。