公开(公告)号：US09281046B2

公开(公告)日：2016-03-08

申请号：US14048212

申请日：2013-10-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl

IPC: G06F13/16 ,  G11C11/406

CPC classification number: G11C11/40603 ,  G06F13/1605 ,  G06F13/1642

Abstract: A data processor includes a memory accessing agent and a memory controller. The memory accessing agent generates a plurality of accesses to a memory. The memory controller is coupled to the memory accessing agent and schedules the plurality of memory accesses in an order based on characteristics of the memory. The characteristics of the memory include a row cycle page time (tRCPAGE) indicative of an acceptable number of activate commands to a row in the memory within a predetermined time window.

Abstract translation: 数据处理器包括存储器访问代理和存储器控制器。 存储器访问代理生成对存储器的多个访问。 存储器控制器耦合到存储器访问代理，并且基于存储器的特性按顺序调度多个存储器访问。 存储器的特性包括在预定时间窗口内指示存储器中的行的可接受数量的激活命令的行周期寻呼时间（tRCPAGE）。

公开(公告)号：US20150100723A1

公开(公告)日：2015-04-09

申请号：US14048212

申请日：2013-10-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl

IPC: G11C11/406

CPC classification number: G11C11/40603 ,  G06F13/1605 ,  G06F13/1642

Abstract: A data processor includes a memory accessing agent and a memory controller. The memory accessing agent generates a plurality of accesses to a memory. The memory controller is coupled to the memory accessing agent and schedules the plurality of memory accesses in an order based on characteristics of the memory. The characteristics of the memory include a row cycle page time (tRCPAGE) indicative of an acceptable number of activate commands to a row in the memory within a predetermined time window.

Abstract translation: 数据处理器包括存储器访问代理和存储器控制器。 存储器访问代理生成对存储器的多个访问。 存储器控制器耦合到存储器访问代理，并且基于存储器的特性按顺序调度多个存储器访问。 存储器的特性包括在预定时间窗口内指示存储器中的行的可接受数量的激活命令的行周期寻呼时间（tRCPAGE）。

公开(公告)号：US20150089168A1

公开(公告)日：2015-03-26

申请号：US14032887

申请日：2013-09-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Brandl ,  Adnan Dhanani

IPC: G06F12/06

CPC classification number: G06F12/0607

Abstract: A system and method for mapping an address space to a non-power-of-two number of memory channels. Addresses are translated and interleaved to the memory channels such that each memory channel has an equal amount of mapped address space. The address space is partitioned into two regions, and a first translation function is used for memory requests targeting the first region and a second translation function is used for memory requests targeting the second region. The first translation function is based on a first set of address bits and the second translation function is based on a second set of address bits.

Abstract translation: 一种用于将地址空间映射到非功率数量的存储器通道的系统和方法。 地址被转换并交错到存储器通道，使得每个存储器通道具有相等量的映射地址空间。 地址空间被划分成两个区域，并且第一翻译函数用于针对第一区域的存储器请求，并且第二翻译函数用于针对第二区域的存储器请求。 第一翻译函数基于第一组地址位，第二翻译函数基于第二组地址位。

公开(公告)号：US20250004651A1

公开(公告)日：2025-01-02

申请号：US18216109

申请日：2023-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Jean J. Chittilappilly ,  Tahsin Askar ,  James R. Magro

IPC: G06F3/06

Abstract: A memory accessing circuit includes a memory controller for scheduling accesses to a memory, and a physical interface circuit for driving signals to the memory according to scheduled accesses and having configuration data. The memory controller comprises a memory and is responsive to a low power mode entry signal to save the configuration data in the memory. The physical interface circuit removes operating power from circuitry in the physical interface circuit that stores the configuration data in response to the memory controller completing a save operation.

公开(公告)号：US11809743B2

公开(公告)日：2023-11-07

申请号：US17027375

申请日：2020-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0652 ,  G06F3/0673

Abstract: A memory controller includes a command queue having a first input for receiving memory access requests, and a memory interface queue having an output for coupling to a memory channel adapted for connecting to at least one dynamic random access memory (DRAM) module. A refresh control circuit monitors activate commands to be sent over the memory channel. In response to an activate command meeting a designated condition, the refresh control circuit identifies a candidate aggressor row associated with the activate command. A command is sent to the DRAM requesting that the candidate aggressor row be queued for mitigation in a future refresh or refresh management event.

公开(公告)号：US11526278B2

公开(公告)日：2022-12-13

申请号：US15851414

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  James Raymond Magro ,  Kedarnath Balakrishnan ,  Kevin M. Brandl

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes one or more computing resources and a memory controller coupled to a memory device. The memory controller determines a memory access request targets a given bank of multiple banks. An access history is updated for the given bank based on whether the memory access request hits on an open page within the given bank and a page hit rate for the given bank is determined. The memory controller sets an idle cycle limit based on the page hit rate. The idle cycle limit is a maximum amount of time the given bank will be held open before closing the given bank while the bank is idle. The idle cycle limit is based at least in part on a page hit rate for the bank.

公开(公告)号：US20220076739A1

公开(公告)日：2022-03-10

申请号：US17526429

申请日：2021-11-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Naveen Davanam ,  Oswin E. Housty

IPC: G11C11/406 ,  G06F12/02 ,  G06F13/40 ,  G06F13/16 ,  G06F1/3234

Abstract: A system and method for use in dynamic random-access memory (DRAM) comprising entering into a self-refresh mode of operation, exiting the self-refresh mode of operation in response to commands from a self-refresh state machine memory operation (MOP) array, and updating a device state of the DRAM for a target power management state in response to commands from the MOP array.

公开(公告)号：US11222685B2

公开(公告)日：2022-01-11

申请号：US16875281

申请日：2020-05-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Kedarnath Balakrishnan ,  Jing Wang ,  Guanhao Shen

IPC: G06F13/28 ,  G11C11/406

Abstract: A memory controller interfaces with a dynamic random access memory (DRAM) over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

公开(公告)号：US20190196996A1

公开(公告)日：2019-06-27

申请号：US15851087

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Ravindra N. Bhargava ,  Guanhao Shen ,  James Raymond Magro ,  Kevin M. Brandl

IPC: G06F13/30 ,  G06F13/16 ,  G06F3/06

CPC classification number: G06F13/30 ,  G06F3/061 ,  G06F3/0659 ,  G06F13/1642 ,  G06F13/1668

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory read requests have been sent to a memory device in a read mode of a data bus, the memory controller determines a threshold number of memory write requests to send to the memory device in an upcoming write mode is a number of outstanding memory write requests. Alternatively, the memory controller determines the threshold number of memory write requests to send to the memory device in an upcoming write mode is a maximum value of the number of outstanding memory write requests and a programmable value of the write burst length stored in a control register. Therefore, the write burst length is determined dynamically. Similarly, the read burst length is determined dynamically when the write mode ends.

公开(公告)号：US20190196720A1

公开(公告)日：2019-06-27

申请号：US15851414

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  James Raymond Magro ,  Kedarnath Balakrishnan ,  Kevin M. Brandl

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0658 ,  G06F3/0673

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes one or more computing resources and a memory controller coupled to a memory device. The memory controller determines a memory access request targets a given bank of multiple banks. An access history is updated for the given bank based on whether the memory access request hits on an open page within the given bank and a page hit rate for the given bank is determined. The memory controller sets an idle cycle limit based on the page hit rate. The idle cycle limit is a maximum amount of time the given bank will be held open before closing the given bank while the bank is idle. The idle cycle limit is based at least in part on a page hit rate for the bank.