公开(公告)号：US20230101748A1

公开(公告)日：2023-03-30

申请号：US17490910

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0811 ,  G06F12/0875 ,  G06F12/0808

Abstract: Techniques for invalidating cache lines are provided. The techniques include issuing, to a first level of a memory hierarchy, a weak exclusive read request for a speculatively executing store instruction; determining whether to invalidate one or more cache lines associated with the store instruction in one or more memories; and issuing the weak invalidation request to additional levels of the memory hierarchy.

公开(公告)号：US12189530B2

公开(公告)日：2025-01-07

申请号：US18621799

申请日：2024-03-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/08 ,  G06F12/0802

Abstract: Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.

公开(公告)号：US12099451B2

公开(公告)日：2024-09-24

申请号：US17489726

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/127

CPC classification number: G06F12/122 ,  G06F12/123 ,  G06F12/124 ,  G06F12/127 ,  G06F2212/60

Abstract: Systems and methods for cache replacement are disclosed. Techniques are described that determine a re-reference interval prediction (RRIP) value of respective data blocks in a cache, where an RRIP value represents a likelihood that a respective data block will be re-used within a time interval. Upon an access, by a processor, to a data segment in a memory, if the data segment is not stored in the cache, a data block in the cache to be replaced by the data segment is selected, utilizing a binary tree that tracks recency of data blocks in the cache.

公开(公告)号：US11868221B2

公开(公告)日：2024-01-09

申请号：US17490862

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kelley ,  Vanchinathan Venkataramani ,  Paul J. Moyer

IPC: G06F11/00 ,  G06F11/263 ,  G06F11/30 ,  G06F11/07 ,  G06F11/34

CPC classification number: G06F11/263 ,  G06F11/076 ,  G06F11/3037 ,  G06F11/3409 ,  G06F11/3457

Abstract: Techniques for performing cache operations are provided. The techniques include tracking performance events for a plurality of test sets of a cache, detecting a replacement policy change trigger event associated with a test set of the plurality of test sets, and in response to the replacement policy change trigger event, operating non-test sets of the cache according to a replacement policy associated with the test set.

公开(公告)号：US20230138518A1

公开(公告)日：2023-05-04

申请号：US17514776

申请日：2021-10-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0891 ,  G06F12/084 ,  G06F13/16 ,  G06F9/30

Abstract: Techniques for performing cache operations are provided. The techniques include for a memory access class, detecting a threshold number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state; in response to the detecting, treating first coherence state agnostic requests for cache lines for the memory access class as requests for cache lines in a shared state; detecting a reset event for the memory access class; and in response to detecting the reset event, treating second coherence state agnostic requests for cache lines for the memory class as coherence state agnostic requests.

公开(公告)号：US20230099256A1

公开(公告)日：2023-03-30

申请号：US17489712

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0817

Abstract: A system and method for omission of probes when requesting data stored in memory where the omission includes creating a coherence directory entry, determining whether cache line data for the coherence directory entry is a trackable pattern, and setting an indication indicating that one or more reads for the cache line data can be serviced without sending probes. A system and method for providing extra data storage capacity in a coherence directory where the extra data storage capacity includes actively tracking cache lines, invalidating the cache line and informing the coherence directory, determining whether data is a trackable pattern, updating the coherence directory that the cache line is no longer in cache, updating the coherence directory to indicate cache line data is zero, and servicing reads to the cache line from the coherence directory and supplying the specified data.

公开(公告)号：US20230096563A1

公开(公告)日：2023-03-30

申请号：US17489702

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0802

Abstract: Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.

公开(公告)号：US20240241827A1

公开(公告)日：2024-07-18

申请号：US18621799

申请日：2024-03-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.

公开(公告)号：US11947456B2

公开(公告)日：2024-04-02

申请号：US17490910

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/00 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0875

CPC classification number: G06F12/0811 ,  G06F12/0808 ,  G06F12/0875

Abstract: Techniques for invalidating cache lines are provided. The techniques include issuing, to a first level of a memory hierarchy, a weak exclusive read request for a speculatively executing store instruction; determining whether to invalidate one or more cache lines associated with the store instruction in one or more memories; and issuing the weak invalidation request to additional levels of the memory hierarchy.

公开(公告)号：US11822479B2

公开(公告)日：2023-11-21

申请号：US17514811

申请日：2021-10-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/08 ,  G06F12/0891

CPC classification number: G06F12/0891 ,  G06F2212/683

Abstract: Techniques for performing cache operations are provided. The techniques include recording an indication that providing exclusive access of a first cache line to a first processor is deemed problematic; detecting speculative execution of a store instruction by the first processor to the first cache line; and in response to the detecting, refusing to provide exclusive access of the first cache line to the first processor, based on the indication.