公开(公告)号：US20190057809A1

公开(公告)日：2019-02-21

申请号：US15680059

申请日：2017-08-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan KUNG ,  Hung-Yi LIN ,  Teck-Chong LEE ,  Sheng-Chi HSIEH ,  Chien-Hua CHEN

IPC: H01F27/40 ,  H01F21/12 ,  H01F27/28 ,  H01F27/29 ,  H03H7/38 ,  H01L25/16

Abstract: An electrical device comprises a substrate, a first dielectric layer, a first die, an adjustable inductor and a second die. The substrate has a first surface. The first dielectric layer is disposed on the first surface of the substrate and has a first surface. The first die is surrounded by the first dielectric layer. The adjustable inductor is electrically connected to the first die. The adjustable inductor comprises a plurality of pillars surrounded by the first dielectric layer, a plurality of first metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars, and a plurality of second metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars. A width of at least one of the second metal strips is different than a width of at least one of the first metal strips. The second die is electrically connected to the adjustable inductor.

公开(公告)号：US20210202336A1

公开(公告)日：2021-07-01

申请号：US16730382

申请日：2019-12-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Teck-Chong LEE

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes a wiring structure, at least one electronic device, a reinforcement structure, a plurality of conductive vias and an encapsulant. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The electronic device is electrically connected to the wiring structure. The reinforcement structure is disposed on a surface of the wiring structure, and includes a thermoset material. The conductive vias is disposed in the reinforcement structure. The encapsulant covers the electronic device.

公开(公告)号：US20210043719A1

公开(公告)日：2021-02-11

申请号：US17083281

申请日：2020-10-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE

IPC: H01L49/02 ,  H01L23/522

Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

公开(公告)号：US20200381345A1

公开(公告)日：2020-12-03

申请号：US16427197

申请日：2019-05-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Teck-Chong LEE ,  Wei-Hong LAI ,  Meng-Kai SHIH

IPC: H01L23/498 ,  H01L25/11 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor device package includes a carrier, a conductive pillar and a first package body. The carrier has a first surface and a second surface opposite to the first surface. The conductive pillar is disposed on the second surface of the carrier. The first package is disposed on the second surface of the carrier and covers at least a portion of the conductive pillar. The conductive pillar has an uneven width.

公开(公告)号：US20190393297A1

公开(公告)日：2019-12-26

申请号：US16447839

申请日：2019-06-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan KUNG ,  Chien-Hua CHEN ,  Teck-Chong LEE ,  Hung-Yi LIN ,  Pao-Nan LEE ,  Hsin Hsiang WANG ,  Min-Tzu HSU ,  Po-Hao CHEN

IPC: H01L49/02 ,  H01L25/16 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

公开(公告)号：US20180138262A1

公开(公告)日：2018-05-17

申请号：US15351265

申请日：2016-11-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01L23/147 ,  H01L23/15 ,  H01L23/522 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13111 ,  H01L2924/14

Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

公开(公告)号：US20170133360A1

公开(公告)日：2017-05-11

申请号：US15406530

申请日：2017-01-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Teck-Chong LEE ,  Chien-Hua CHEN ,  Yung-Shun CHANG ,  Pao-Nan LEE

IPC: H01L27/01 ,  H01L23/528 ,  H01L21/70 ,  H01L49/02

CPC classification number: H01L27/016 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/707 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/528 ,  H01L28/10 ,  H01L28/60 ,  H01L2224/4813 ,  H05K1/0306 ,  H05K1/185 ,  H05K2201/0154

Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

公开(公告)号：US20150349048A1

公开(公告)日：2015-12-03

申请号：US14724522

申请日：2015-05-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Teck-Chong LEE ,  Chien-Hua CHEN ,  Yung-Shun CHANG ,  Pao-Nan LEE

IPC: H01L49/02 ,  H01L21/283

CPC classification number: H01L27/016 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/707 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/528 ,  H01L28/10 ,  H01L28/60 ,  H01L2224/4813 ,  H05K1/0306 ,  H05K1/185 ,  H05K2201/0154

Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

Abstract translation: 半导体器件包括衬底，种子层，第一图案化金属层，电介质层和第二金属层。 种子层设置在基板的表面上。 第一图案化金属层设置在种子层上并具有第一厚度。 第一图案化金属层包括第一部分和第二部分。 电介质层设置在第一图案化金属层的第一部分上。 第二金属层设置在电介质层上，具有第二厚度，其中第一厚度大于第二厚度。 第一图案化金属层的第一部分，电介质层和第二金属层形成电容器。 第一图案化金属层的第一部分是电容器的下电极，第一图案化金属层的第二部分是电感器。

公开(公告)号：US20230197600A1

公开(公告)日：2023-06-22

申请号：US17555227

申请日：2021-12-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Sheng-Wen YANG ,  Teck-Chong LEE ,  Yen-Liang HUANG

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/12

CPC classification number: H01L23/5226 ,  H01L23/31 ,  H01L23/12

Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.

公开(公告)号：US20220068839A1

公开(公告)日：2022-03-03

申请号：US17003883

申请日：2020-08-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Po-Hsien KE ,  Teck-Chong LEE ,  Chih-Pin HUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.