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    HYBRID DUAL MATCH LINE ARCHITECTURE FOR CONTENT ADDRESSABLE MEMORIES AND OTHER DATA STRUCTURES
    11.
    发明申请
    HYBRID DUAL MATCH LINE ARCHITECTURE FOR CONTENT ADDRESSABLE MEMORIES AND OTHER DATA STRUCTURES 失效
    用于内容可寻址存储器和其他数据结构的混合双匹配线架构

    公开(公告)号：US20080239778A1

    公开(公告)日：2008-10-02

    申请号：US11695395

    申请日：2007-04-02

    申请人： Shashank Shastry ,  Sagar V. Reddy ,  Ajay Bhatia

    发明人： Shashank Shastry ,  Sagar V. Reddy ,  Ajay Bhatia

    IPC分类号： G11C15/04 ,  G06F12/02 ,  G11C15/00

    CPC分类号： G11C15/04 ,  G06F7/02 ,  G06F12/0895 ,  G06F12/1027

    摘要： A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an asserted state. Each of the second group of load devices may be activated for discharging by a respective miss signal. The hit match line may be additionally coupled to discharge through first and second discharge path respectively activated for discharging in response to a hit signal and a read/write enable signal. The hit and miss match lines may be electrically isolated from one another, such that when one or more of the respective miss signals are asserted, current from the hit match line does not discharge through the miss match line.

    摘要翻译： 混合双匹配线路电路可以包括耦合到第一组负载装置的匹配匹配线和耦合到通过第二组负载装置放电的未匹配线。 命中和未命中匹配线都可以被配置为预充电到断言状态。 可以通过相应的未命中信号来激活第二组负载装置中的每一个以进行放电。 命中匹配线可以另外耦合到通过响应于命中信号和读/写使能信号分别被激活以用于放电的第一和第二放电路径放电。 命中和未命中匹配线可以彼此电隔离，使得当相应的未命中信号中的一个或多个被断言时，来自命中匹配线的电流不会通过未命中匹配线放电。

    Race condition improvements in dual match line architectures
    13.
    发明授权
    Race condition improvements in dual match line architectures 有权
    双匹配线路架构中的竞争状况改善

    公开(公告)号：US07203082B1

    公开(公告)日：2007-04-10

    申请号：US11144123

    申请日：2005-05-31

    申请人： Ajay Bhatia ,  Sanjay M. Wanzakhade ,  Shashank Shastry

    发明人： Ajay Bhatia ,  Sanjay M. Wanzakhade ,  Shashank Shastry

    IPC分类号： G11C15/04 ,  G06F12/00

    CPC分类号： G11C15/04 ,  G06F12/0895 ,  G06F12/1027 ,  Y02D10/13

    摘要： Dual match line circuits having race condition improvements. A dual match line circuit may include precharge logic configured to precharge each of a hit match line, a miss match line and an evaluate node to an asserted state, where a coupling device couples the hit and miss match lines to the evaluate node. The miss match line may discharge through a number of load devices that may be activated by respective miss signals. A positive feedback circuit coupled to the miss match line may accelerate its discharge. The hit match line may be additionally coupled to discharge through a discharge path. The hit and miss match lines may be electrically isolated from one another, such that when any of the respective miss signals is asserted, current from the hit match line does not discharge through the miss match line.

    摘要翻译： 具有竞争条件改进的双匹配线路电路。 双匹配线路电路可以包括预充电逻辑，其被配置为将命中匹配线，未命中匹配线和评估节点中的每一个预先充电到断言状态，其中耦合设备将命中和未命中匹配线耦合到评估节点。 错过匹配线可以通过可能由相应的未命中信号激活的多个负载装置放电。 耦合到未匹配线的正反馈电路可以加速其放电。 命中匹配线可以另外耦合以通过放电路径放电。 命中和未命中匹配线可以彼此电隔离，使得当相应的未命中信号中的任一个被断言时，来自命中匹配线的电流不会通过未命中匹配线放电。

    Memory device with split power switch
    17.
    发明授权
    Memory device with split power switch 有权
    带有分离电源开关的存储器件

    公开(公告)号：US07952910B2

    公开(公告)日：2011-05-31

    申请号：US11932555

    申请日：2007-10-31

    申请人： Yolin Lih ,  Dennis Wendell ,  Jun Liu ,  Daniel Fung ,  Ajay Bhatia ,  Shyam Balasubramanian

    发明人： Yolin Lih ,  Dennis Wendell ,  Jun Liu ,  Daniel Fung ,  Ajay Bhatia ,  Shyam Balasubramanian

    IPC分类号： G11C11/00

    CPC分类号： G11C11/419 ,  G11C5/147 ,  G11C11/417

    摘要： A memory device having a split power switch is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various split power switch circuits are used to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state.

    摘要翻译： 提供具有分离电源开关的存储器件以提高静态随机存取存储器（SRAM）单元的可写性，而不会不利地影响其稳定性。 例如，各种分离电源开关电路用于允许在写操作期间与SRAM单元的一侧连接的电源线的电压或电流下降。 该电压降弱了SRAM单元的一侧，并减少了SRAM单元的晶体管与外部写入电路之间的驱动。 结果，将新的逻辑状态写入SRAM单元的最小电压被降低以允许SRAM单元和相关电路的总体较低工作电压。 通过继续以参考电压或电流保持SRAM单元的第二面，SRAM单元可以成功切换到新写入的逻辑状态。

    DYNAMIC DUAL OUTPUT LATCH
    18.
    发明申请
    DYNAMIC DUAL OUTPUT LATCH 有权
    动态双输出锁

    公开(公告)号：US20080258788A1

    公开(公告)日：2008-10-23

    申请号：US11738287

    申请日：2007-04-20

    申请人： Ajay Bhatia ,  Uttam Saha

    发明人： Ajay Bhatia ,  Uttam Saha

    IPC分类号： H03K3/037

    CPC分类号： H03K5/1515 ,  H03K3/356121 ,  H03K19/0963

    摘要： A dynamic latch includes a first stage for receiving an input data value and for providing true and complement logic values representing the input data value; a second stage for receiving the true and complement logic values into first and second dynamic node, when a control signal is active; and a holding that outputs the true and complement logic values while the control signal is active. The second stage may provide a feedback signal to the first stage to block propagation of changes in the input data value after the true and complement logic values have been received. The feedback signal may be derived, for example, from logic values on the dynamic nodes. A holding circuit may be provided.

    摘要翻译： 动态锁存器包括用于接收输入数据值并提供表示输入数据值的真实和补码逻辑值的第一级; 第二阶段，当控制信号有效时，接收真实和补充逻辑值到第一和第二动态节点; 以及在控制信号有效时输出真实和补码逻辑值的保持。 第二级可以在接收到真实和补码逻辑值之后，向第一级提供反馈信号以阻止输入数据值中变化的传播。 反馈信号可以例如从动态节点上的逻辑值导出。 可以提供保持电路。

    Dual match line architecture for content addressable memories and other data structures
    19.
    发明授权
    Dual match line architecture for content addressable memories and other data structures 有权
    双匹配线架构，用于内容可寻址存储器和其他数据结构

    公开(公告)号：US07200019B1

    公开(公告)日：2007-04-03

    申请号：US11141301

    申请日：2005-05-31

    申请人： Ajay Bhatia ,  Sanjay M. Wanzakhade ,  Shashank Shastry

    发明人： Ajay Bhatia ,  Sanjay M. Wanzakhade ,  Shashank Shastry

    IPC分类号： G11C15/04 ,  G06F12/00

    CPC分类号： G11C15/04 ,  G06F12/1009 ,  Y02D10/13

    摘要： A dual match line circuit may include precharge logic configured to precharge each of a hit match line, a miss match line and an evaluate node to an asserted state, where a coupling device couples the hit and miss match lines to the evaluate node. The miss match line may discharge through a number of load devices that may be activated by respective miss signals. The hit match line may be additionally coupled to discharge through a pair of devices connected in series, one of which may be activated by a hit signal, and the other of which may be activated by the miss match line. The hit and miss match lines may be electrically isolated from one another, such that when any of the respective miss signals is asserted, current from the hit match line does not discharge through the miss match line.

    摘要翻译： 双匹配线路电路可以包括预充电逻辑，其被配置为将命中匹配线，未命中匹配线和评估节点中的每一个预先充电到断言状态，其中耦合设备将命中和未命中匹配线耦合到评估节点。 错过匹配线可以通过可能由相应的未命中信号激活的多个负载装置放电。 命中匹配线可以另外耦合以通过串联连接的一对装置放电，其中一个可以由命中信号激活，并且另一个可以由未匹配线激活。 命中和未命中匹配线可以彼此电隔离，使得当相应的未命中信号中的任一个被断言时，来自命中匹配线的电流不会通过未命中匹配线放电。

    System and method for a self-calibrating sense-amplifier strobe
    20.
    发明授权
    System and method for a self-calibrating sense-amplifier strobe 有权
    用于自校准读出放大器选通的系统和方法

    公开(公告)号：US06714464B2

    公开(公告)日：2004-03-30

    申请号：US10180478

    申请日：2002-06-26

    申请人： Ajay Bhatia ,  Michael C. Braganza ,  Shannon V. Morton ,  Shashank Shastry

    发明人： Ajay Bhatia ,  Michael C. Braganza ,  Shannon V. Morton ,  Shashank Shastry

    IPC分类号： G11C700

    CPC分类号： G11C7/222 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/065 ,  G11C2207/2254

    摘要： A system and method for self-calibration of the strobe timing of the sense-amplifiers of a RAM array. In one method example, the timing of two sense amplifiers used to read the bit-lines of the RAM array is controlled by a Delay Locked Loop circuit (DLL). The timing of a first sense-amplifier strobe is reduced until the sense amplifier fails. The second sense amplifier has adequate timing margin however and is used to actually read the RAM bit-lines. Once the RAM read fails with the first sense amplifier, the DLL lengthens the strobe timing. Once the minimum threshold is set, the second sense amplifier will always read the correct data because of a built-in timing margin between the first and second amplifier. Thus the system constantly optimizes the RAM array read timing with each read cycle even though the minimal time varies.

    摘要翻译： 用于RAM阵列的读出放大器的选通定时的自校准的系统和方法。 在一个方法示例中，用于读取RAM阵列的位线的两个读出放大器的定时由延迟锁定环电路（DLL）控制。 第一感测放大器选通脉冲的定时降低，直到读出放大器发生故障。 然而，第二感测放大器具有足够的定时裕度，并用于实际读取RAM位线。 一旦RAM读取失败，第一个读出放大器，DLL会延长选通时序。 一旦设置了最小阈值，由于第一和第二放大器之间的内置定时裕度，第二读出放大器将始终读取正确的数据。 因此，即使最小时间变化，系统也会随着每个读取周期不断优化RAM阵列读取定时。