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    DYNAMIC DUAL OUTPUT LATCH
    1.
    发明申请
    DYNAMIC DUAL OUTPUT LATCH 有权
    动态双输出锁

    公开(公告)号：US20080258788A1

    公开(公告)日：2008-10-23

    申请号：US11738287

    申请日：2007-04-20

    申请人： Ajay Bhatia ,  Uttam Saha

    发明人： Ajay Bhatia ,  Uttam Saha

    IPC分类号： H03K3/037

    CPC分类号： H03K5/1515 ,  H03K3/356121 ,  H03K19/0963

    摘要： A dynamic latch includes a first stage for receiving an input data value and for providing true and complement logic values representing the input data value; a second stage for receiving the true and complement logic values into first and second dynamic node, when a control signal is active; and a holding that outputs the true and complement logic values while the control signal is active. The second stage may provide a feedback signal to the first stage to block propagation of changes in the input data value after the true and complement logic values have been received. The feedback signal may be derived, for example, from logic values on the dynamic nodes. A holding circuit may be provided.

    摘要翻译： 动态锁存器包括用于接收输入数据值并提供表示输入数据值的真实和补码逻辑值的第一级; 第二阶段，当控制信号有效时，接收真实和补充逻辑值到第一和第二动态节点; 以及在控制信号有效时输出真实和补码逻辑值的保持。 第二级可以在接收到真实和补码逻辑值之后，向第一级提供反馈信号以阻止输入数据值中变化的传播。 反馈信号可以例如从动态节点上的逻辑值导出。 可以提供保持电路。

    Dynamic dual output latch
    2.
    发明授权
    Dynamic dual output latch 有权
    动态双输出锁存器

    公开(公告)号：US07710155B2

    公开(公告)日：2010-05-04

    申请号：US11738287

    申请日：2007-04-20

    申请人： Ajay Bhatia ,  Uttam Saha

    发明人： Ajay Bhatia ,  Uttam Saha

    IPC分类号： H03K19/00 ,  H03K19/096

    CPC分类号： H03K5/1515 ,  H03K3/356121 ,  H03K19/0963

    摘要： A dynamic latch includes a first stage for receiving an input data value and for providing true and complement logic values representing the input data value; a second stage for receiving the true and complement logic values into first and second dynamic node, when a control signal is active; and a holding that outputs the true and complement logic values while the control signal is active. The second stage may provide a feedback signal to the first stage to block propagation of changes in the input data value after the true and complement logic values have been received. The feedback signal may be derived, for example, from logic values on the dynamic nodes. A holding circuit may be provided.

    摘要翻译： 动态锁存器包括用于接收输入数据值并提供表示输入数据值的真实和补码逻辑值的第一级; 第二阶段，当控制信号有效时，接收真实和补充逻辑值到第一和第二动态节点; 以及在控制信号有效时输出真实和补码逻辑值的保持。 第二级可以在接收到真实和补码逻辑值之后，向第一级提供反馈信号以阻止输入数据值中变化的传播。 反馈信号可以例如从动态节点上的逻辑值导出。 可以提供保持电路。

    DYNAMIC VOLTAGE SCALING FOR SELF-TIMED OR RACING PATHS
    3.
    发明申请
    DYNAMIC VOLTAGE SCALING FOR SELF-TIMED OR RACING PATHS 有权
    自动或赛车运动的动态电压调节

    公开(公告)号：US20090108899A1

    公开(公告)日：2009-04-30

    申请号：US11932311

    申请日：2007-10-31

    申请人： Ajay Bhatia ,  Rajesh Khanna

    发明人： Ajay Bhatia ,  Rajesh Khanna

    IPC分类号： H03H11/26 ,  G06F17/50

    CPC分类号： H03H11/265 ,  G11C7/04 ,  G11C7/08 ,  G11C7/22 ,  G11C11/4076 ,  H03K19/00384 ,  H03K19/018521 ,  H03K2005/00019

    摘要： A timing-constrained circuit (e.g., a self-timed circuit) of optimal performance is achieved by allowing the delay of the circuit to be changed dynamically as a function of operating conditions (e.g., operating voltages or temperatures). The delay of timing signals in the timing-constrained circuit for a given operating condition may be selected to have the minimum margin for that operating condition among the available delays to maximize performance over the entire dynamic range of operating conditions.

    摘要翻译： 通过允许根据操作条件（例如，工作电压或温度）动态地改变电路的延迟来实现具有最佳性能的定时受限电路（例如，自定时电路）。 可以选择给定操作条件的定时约束电路中的定时信号的延迟，以便在可用延迟之间具有该操作条件的最小余量，以在整个操作条件的动态范围内最大化性能。

    COMPOUNDS AND METHODS FOR TREATMENT AND DIAGNOSIS OF CHLAMYDIAL INFECTION
    5.
    发明申请
    COMPOUNDS AND METHODS FOR TREATMENT AND DIAGNOSIS OF CHLAMYDIAL INFECTION 有权
    用于治疗和诊断CHLAMYDIAL感染的化合物和方法

    公开(公告)号：US20080299142A1

    公开(公告)日：2008-12-04

    申请号：US11929665

    申请日：2007-10-30

    申请人： Ajay Bhatia ,  Yasir A.W. Skeiky ,  Peter Probst

    发明人： Ajay Bhatia ,  Yasir A.W. Skeiky ,  Peter Probst

    IPC分类号： A61K39/00 ,  A61P31/00

    CPC分类号： C07K14/295 ,  A61K38/00 ,  A61K39/00 ,  A61K48/00 ,  A61K2039/505 ,  A61K2039/51 ,  A61K2039/515 ,  A61K2039/5154 ,  A61K2039/53 ,  C07K2319/00

    摘要： Compounds and methods for the diagnosis and treatment of Chlamydial infection are disclosed. The compounds provided include polypeptides that contain at least one antigenic portion of a Chlamydia antigen and DNA sequences encoding such polypeptides. Pharmaceutical compositions and vaccines comprising such polypeptides or DNA sequences are also provided, together with antibodies directed against such polypeptides. Diagnostic kits containing such polypeptides or DNA sequences and a suitable detection reagent may be used for the detection of Chlamydial infection in patients and in biological samples.

    摘要翻译： 公开了用于诊断和治疗衣原体感染的化合物和方法。 提供的化合物包括含有衣原体抗原的至少一个抗原部分的多肽和编码这些多肽的DNA序列。 还提供了包含此类多肽或DNA序列的药物组合物和疫苗以及针对这些多肽的抗体。 含有此类多肽或DNA序列的诊断试剂盒和合适的检测试剂可用于检测患者和生物样品中的衣原体感染。

    MEMORY DEVICE WITH SPLIT POWER SWITCH
    6.
    发明申请
    MEMORY DEVICE WITH SPLIT POWER SWITCH 有权
    具有分离电源开关的存储器件

    公开(公告)号：US20080273412A1

    公开(公告)日：2008-11-06

    申请号：US11932555

    申请日：2007-10-31

    申请人： Yolin Lih ,  Dennis Wendell ,  Jun Liu ,  Daniel Fung ,  Ajay Bhatia ,  Shyam Balasubramanian

    发明人： Yolin Lih ,  Dennis Wendell ,  Jun Liu ,  Daniel Fung ,  Ajay Bhatia ,  Shyam Balasubramanian

    IPC分类号： G11C5/14

    CPC分类号： G11C11/419 ,  G11C5/147 ,  G11C11/417

    摘要： A memory device having a split power switch is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various split power switch circuits are used to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state.

    摘要翻译： 提供具有分离电源开关的存储器件以提高静态随机存取存储器（SRAM）单元的可写性，而不会不利地影响其稳定性。 例如，各种分离电源开关电路用于允许在写操作期间与SRAM单元的一侧连接的电源线的电压或电流下降。 该电压降弱了SRAM单元的一侧，并减少了SRAM单元的晶体管与外部写入电路之间的驱动。 结果，将新的逻辑状态写入SRAM单元的最小电压被降低以允许SRAM单元和相关电路的总体较低工作电压。 通过继续以参考电压或电流保持SRAM单元的第二面，SRAM单元可以成功切换到新写入的逻辑状态。

    HYBRID DUAL MATCH LINE ARCHITECTURE FOR CONTENT ADDRESSABLE MEMORIES AND OTHER DATA STRUCTURES
    7.
    发明申请
    HYBRID DUAL MATCH LINE ARCHITECTURE FOR CONTENT ADDRESSABLE MEMORIES AND OTHER DATA STRUCTURES 失效
    用于内容可寻址存储器和其他数据结构的混合双匹配线架构

    公开(公告)号：US20080239778A1

    公开(公告)日：2008-10-02

    申请号：US11695395

    申请日：2007-04-02

    申请人： Shashank Shastry ,  Sagar V. Reddy ,  Ajay Bhatia

    发明人： Shashank Shastry ,  Sagar V. Reddy ,  Ajay Bhatia

    IPC分类号： G11C15/04 ,  G06F12/02 ,  G11C15/00

    CPC分类号： G11C15/04 ,  G06F7/02 ,  G06F12/0895 ,  G06F12/1027

    摘要： A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an asserted state. Each of the second group of load devices may be activated for discharging by a respective miss signal. The hit match line may be additionally coupled to discharge through first and second discharge path respectively activated for discharging in response to a hit signal and a read/write enable signal. The hit and miss match lines may be electrically isolated from one another, such that when one or more of the respective miss signals are asserted, current from the hit match line does not discharge through the miss match line.

    摘要翻译： 混合双匹配线路电路可以包括耦合到第一组负载装置的匹配匹配线和耦合到通过第二组负载装置放电的未匹配线。 命中和未命中匹配线都可以被配置为预充电到断言状态。 可以通过相应的未命中信号来激活第二组负载装置中的每一个以进行放电。 命中匹配线可以另外耦合到通过响应于命中信号和读/写使能信号分别被激活以用于放电的第一和第二放电路径放电。 命中和未命中匹配线可以彼此电隔离，使得当相应的未命中信号中的一个或多个被断言时，来自命中匹配线的电流不会通过未命中匹配线放电。

    Race condition improvements in dual match line architectures
    9.
    发明授权
    Race condition improvements in dual match line architectures 有权
    双匹配线路架构中的竞争状况改善

    公开(公告)号：US07203082B1

    公开(公告)日：2007-04-10

    申请号：US11144123

    申请日：2005-05-31

    申请人： Ajay Bhatia ,  Sanjay M. Wanzakhade ,  Shashank Shastry

    发明人： Ajay Bhatia ,  Sanjay M. Wanzakhade ,  Shashank Shastry

    IPC分类号： G11C15/04 ,  G06F12/00

    CPC分类号： G11C15/04 ,  G06F12/0895 ,  G06F12/1027 ,  Y02D10/13

    摘要： Dual match line circuits having race condition improvements. A dual match line circuit may include precharge logic configured to precharge each of a hit match line, a miss match line and an evaluate node to an asserted state, where a coupling device couples the hit and miss match lines to the evaluate node. The miss match line may discharge through a number of load devices that may be activated by respective miss signals. A positive feedback circuit coupled to the miss match line may accelerate its discharge. The hit match line may be additionally coupled to discharge through a discharge path. The hit and miss match lines may be electrically isolated from one another, such that when any of the respective miss signals is asserted, current from the hit match line does not discharge through the miss match line.

    摘要翻译： 具有竞争条件改进的双匹配线路电路。 双匹配线路电路可以包括预充电逻辑，其被配置为将命中匹配线，未命中匹配线和评估节点中的每一个预先充电到断言状态，其中耦合设备将命中和未命中匹配线耦合到评估节点。 错过匹配线可以通过可能由相应的未命中信号激活的多个负载装置放电。 耦合到未匹配线的正反馈电路可以加速其放电。 命中匹配线可以另外耦合以通过放电路径放电。 命中和未命中匹配线可以彼此电隔离，使得当相应的未命中信号中的任一个被断言时，来自命中匹配线的电流不会通过未命中匹配线放电。