公开(公告)号：US07800167B2

公开(公告)日：2010-09-21

申请号：US11802917

申请日：2007-05-25

申请人： Mutsumi Kitamura ,  Akio Sugi ,  Naoto Fujishima ,  Shinichiro Matsunaga

发明人： Mutsumi Kitamura ,  Akio Sugi ,  Naoto Fujishima ,  Shinichiro Matsunaga

IPC分类号： H01L31/119

CPC分类号： H01M10/4207 ,  H01L27/0629 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/781 ,  H01L29/7827 ,  H01M10/48

摘要： A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.

摘要翻译： 双向沟槽横向功率MOSFET（TLPM）可实现高击穿电压和低导通电阻。 在两端具有圆形部分的多个直形岛被沟槽布置包围。 这些岛提供第一n个源区，并且在岛的外部形成第二n源区。 利用这种图案，在第二n个源极区域处于高电位的情况下，在第一n个源极区域处于高电位的情况下的击穿电压可以高于击穿电压。 或者，在不改变击穿电压的情况下，可以降低导通电阻。

公开(公告)号：US20070274110A1

公开(公告)日：2007-11-29

申请号：US11802917

申请日：2007-05-25

申请人： Mutsumi Kitamura ,  Akio Sugi ,  Naoto Fujishima ,  Shinichiro Matsunaga

发明人： Mutsumi Kitamura ,  Akio Sugi ,  Naoto Fujishima ,  Shinichiro Matsunaga

IPC分类号： H02M3/06

CPC分类号： H01M10/4207 ,  H01L27/0629 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/781 ,  H01L29/7827 ,  H01M10/48

摘要： A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.

摘要翻译： 双向沟槽横向功率MOSFET（TLPM）可实现高击穿电压和低导通电阻。 在两端具有圆形部分的多个直形岛被沟槽布置包围。 这些岛提供第一n个源区，并且在岛的外部形成第二n源区。 利用这种图案，在第二n个源极区域处于高电位的情况下，在第一n个源极区域处于高电位的情况下的击穿电压可以高于击穿电压。 或者，在不改变击穿电压的情况下，可以降低导通电阻。

公开(公告)号：US20050062101A1

公开(公告)日：2005-03-24

申请号：US10927434

申请日：2004-08-27

申请人： Akio Sugi ,  Naoto Fujishima

发明人： Akio Sugi ,  Naoto Fujishima

IPC分类号： H01L21/762 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/739 ,  H01L29/94 ,  H01L21/3205

CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7394

摘要： A semiconductor structure with device trench and a semiconductor device in the device trench, that enables realization of high integration, lowered on-resistance, reduction in switching losses and a high operation speed in a semiconductor device provided with a lateral IGBT, and that prevents malfunctions such as latchup when IGBTs or an IGBT and CMOS devices are integrated together. The structure includes an SOI substrate having a supporting substrate, an oxide film and a p−-semiconductor layer. An island-like element-forming region is isolated by a trench isolation region from surroundings. The trench isolation region includes an isolation trench with an insulation film on its inner wall. The device trench is formed in the element-forming region. A gate electrode is formed with a gate insulator film in the device trench. A collector region and an emitter region outside are provided respectively on the bottom and the outside of the device trench.

摘要翻译： 在器件沟槽中具有器件沟槽和半导体器件的半导体结构，能够实现在具有横向IGBT的半导体器件中实现高集成度，降低导通电阻，降低开关损耗以及高操作速度，并且防止故障 例如当IGBT或IGBT和CMOS器件集成在一起时闭锁。 该结构包括具有支撑衬底，氧化膜和p - 半导体层的SOI衬底。 岛状元件形成区域通过与环境的沟槽隔离区隔离。 沟槽隔离区域包括在其内壁上具有绝缘膜的隔离沟槽。 器件沟槽形成在元件形成区域中。 栅电极在器件沟槽中形成有栅极绝缘膜。 分别在器件沟槽的底部和外部设置集电极区域和外部的发射极区域。

公开(公告)号：US09087893B2

公开(公告)日：2015-07-21

申请号：US13575984

申请日：2011-01-28

申请人： Yasuhiko Onishi ,  Mutsumi Kitamura ,  Akio Sugi ,  Manabu Takei

发明人： Yasuhiko Onishi ,  Mutsumi Kitamura ,  Akio Sugi ,  Manabu Takei

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7813

摘要： A parallel p-n layer (20) is provided as a drift layer between an active portion and an n+ drain region (11). The parallel p-n layer (20) is formed by an n-type region (1) and a p-type region (2) being repeatedly alternately joined. An n-type high concentration region (21) is provided on a first main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration higher than that of an n-type low concentration region (22) provided on a second main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (22). Also, the n-type high concentration region (21) has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region (1) adjacent to the p-type region (2).

摘要翻译： 在活性部分和n +漏极区域（11）之间提供平行p-n层（20）作为漂移层。 平行p-n层（20）由n型区域（1）和重复交替接合的p型区域（2）形成。 n型高浓度区域（21）设置在n型区域（1）的第一主表面侧。 n型高浓度区域（21）的杂质浓度高于设置在n型区域（1）的第二主面侧的n型低浓度区域（22）的杂质浓度。 n型高浓度区域（21）的杂质浓度比n型低浓度区域（22）的杂质浓度大1.2倍以上3倍以下，优选为1.5倍以上2.5倍以下。 此外，n型高浓度区域（21）的n区域（1）的相邻区域的厚度的三分之一以下，优选为八分之一以上，四分之一以下。 p型区域（2）。

公开(公告)号：US06781197B2

公开(公告)日：2004-08-24

申请号：US10103543

申请日：2002-03-21

申请人： Naoto Fujishima ,  Akio Sugi ,  C. Andre T. Salama

发明人： Naoto Fujishima ,  Akio Sugi ,  C. Andre T. Salama

IPC分类号： H01L2976

CPC分类号： H01L29/7827 ,  H01L21/823487 ,  H01L29/4236 ,  H01L29/66666

摘要： A trench-type lateral power MOSFET is manufactured by forming an n−-type diffusion region, which will be a drift region, on a p−-type substrate; selectively removing a part of substrate and a part of n−-type diffusion region to form trenches; forming a gate oxide film of 0.05 &mgr;m in thickness in each trench; forming a polycrystalline silicon gate layer on gate oxide film; forming a p−-type base region and an n+-type diffusion region, which will be a source region, in the bottom of each trench; and forming an n+-type diffusion region, which will be a drain region, in the surface portion of n30 -type diffusion region. The MOSFET has reduced device pitch, a reduced on-resistance per unit area and a simplified manufacturing process.

摘要翻译： 沟槽型侧向功率MOSFET通过在p +型衬底上形成作为漂移区域的n +型扩散区域来制造; 选择性地去除衬底的一部分和n +型扩散区的一部分以形成沟槽; 在每个沟槽中形成厚度为0.05μm的栅氧化膜; 在栅极氧化膜上形成多晶硅栅极层; 在每个沟槽的底部形成作为源极区域的p +型基极区域和n +型扩散区域; 并在n30型扩散区的表面部分形成作为漏区的n +型扩散区。 MOSFET减少了器件间距，降低了单位面积的导通电阻，并简化了制造工艺。

公开(公告)号：US07109551B2

公开(公告)日：2006-09-19

申请号：US10927434

申请日：2004-08-27

申请人： Akio Sugi ,  Naoto Fujishima

发明人： Akio Sugi ,  Naoto Fujishima

IPC分类号： H01L29/739 ,  H01L29/78

CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7394

摘要： A semiconductor structure with device trench and a semiconductor device in the device trench, that enables realization of high integration, lowered on-resistance, reduction in switching losses and a high operation speed in a semiconductor device provided with a lateral IGBT, and that prevents malfunctions such as latchup when IGBTs or an IGBT and CMOS devices are integrated together. The structure includes an SOI substrate having a supporting substrate, an oxide film and a p−-semiconductor layer. An island-like element-forming region is isolated by a trench isolation region from surroundings. The trench isolation region includes an isolation trench with an insulation film on its inner wall. The device trench is formed in the element-forming region. A gate electrode is formed with a gate insulator film in the device trench. A collector region and an emitter region outside are provided respectively on the bottom and the outside of the device trench.

摘要翻译： 在器件沟槽中具有器件沟槽和半导体器件的半导体结构，能够实现在具有横向IGBT的半导体器件中实现高集成度，降低导通电阻，降低开关损耗以及高操作速度，并且防止故障 例如当IGBT或IGBT和CMOS器件集成在一起时闭锁。 该结构包括具有支撑衬底，氧化物膜和p型半导体层的SOI衬底。 岛状元件形成区域通过与环境的沟槽隔离区隔离。 沟槽隔离区域包括在其内壁上具有绝缘膜的隔离沟槽。 器件沟槽形成在元件形成区域中。 栅电极在器件沟槽中形成有栅极绝缘膜。 分别在器件沟槽的底部和外部设置集电极区域和外部的发射极区域。

公开(公告)号：US07005352B2

公开(公告)日：2006-02-28

申请号：US10896250

申请日：2004-07-21

申请人： Naoto Fujishima ,  Akio Sugi ,  C. Andre T. Salama

发明人： Naoto Fujishima ,  Akio Sugi ,  C. Andre T. Salama

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L21/823487 ,  H01L29/4236 ,  H01L29/66666

摘要： A trench-type lateral power MOSFET is manufactured by forming an n−-type diffusion region, which will be a drift region, on a p−-type substrate; selectively removing a part of substrate and a part of n−-type diffusion region to form trenches; forming a gate oxide film of 0.05 μm in thickness in each trench; forming a polycrystalline silicon gate layer on gate oxide film; forming a p−-type base region and an n+-type diffusion region, which will be a source region, in the bottom of each trench; and forming an n+-type diffusion region, which will be a drain region, in the surface portion of n−-type diffusion region. The MOSFET has reduced device pitch, a reduced on-resistance per unit area and a simplified manufacturing process.

摘要翻译： 沟槽型侧向功率MOSFET是通过在p型衬底上形成作为漂移区的n + O - 型扩散区制造的; 选择性地去除衬底的一部分和一部分n +型扩散区以形成沟槽; 在每个沟槽中形成厚度为0.05μm的栅氧化膜; 在栅极氧化膜上形成多晶硅栅极层; 在每个沟槽的底部形成作为源极区域的p + H +型基极区域和n + P +型扩散区域; 以及在n型超扩散区域的表面部分中形成作为漏极区域的n + + +型扩散区域。 MOSFET减少了器件间距，降低了单位面积的导通电阻，并简化了制造工艺。

公开(公告)号：US20130026560A1

公开(公告)日：2013-01-31

申请号：US13575984

申请日：2011-01-28

申请人： Yasuhiko Onishi ,  Mutsumi Kitamura ,  Akio Sugi ,  Manabu Takei

发明人： Yasuhiko Onishi ,  Mutsumi Kitamura ,  Akio Sugi ,  Manabu Takei

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7813

摘要： A parallel p-n layer (20) is provided as a drift layer between an active portion and an n+ drain region (11). The parallel p-n layer (20) is formed by an n-type region (1) and a p-type region (2) being repeatedly alternately joined. An n-type high concentration region (21) is provided on a first main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration higher than that of an n-type low concentration region (22) provided on a second main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (22). Also, the n-type high concentration region (21) has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region (1) adjacent to the p-type region (2).

摘要翻译： 在活性部分和n +漏极区域（11）之间提供平行p-n层（20）作为漂移层。 平行p-n层（20）由n型区域（1）和重复交替接合的p型区域（2）形成。 n型高浓度区域（21）设置在n型区域（1）的第一主表面侧。 n型高浓度区域（21）的杂质浓度高于设置在n型区域（1）的第二主面侧的n型低浓度区域（22）的杂质浓度。 n型高浓度区域（21）的杂质浓度比n型低浓度区域（22）的杂质浓度大1.2倍以上3倍以下，优选为1.5倍以上2.5倍以下。 此外，n型高浓度区域（21）的n区域（1）的相邻区域的厚度的三分之一以下，优选为八分之一以上，四分之一以下。 p型区域（2）。

公开(公告)号：US07535059B2

公开(公告)日：2009-05-19

申请号：US11564053

申请日：2006-11-28

申请人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

发明人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

IPC分类号： H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

摘要翻译： 公开了一种包括n型半导体衬底，p型沟道区和设置在n型半导体衬底和p型沟道区之间的结层的半导体器件。 接合层具有与n型半导体衬底的主表面平行的方向交替布置的n型漂移区和p型隔离区。 形成结层的p型分隔区的杂质浓度比n型漂移区高。 这使得半导体器件具有增强的击穿电压，并且同时具有降低的导通电阻。

公开(公告)号：US20120126315A1

公开(公告)日：2012-05-24

申请号：US13313583

申请日：2011-12-07

申请人： Yasuhiko ONISHI ,  Akio Sugi

发明人： Yasuhiko ONISHI ,  Akio Sugi

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741

摘要： A semiconductor apparatus that has a first parallel pn-layer formed between an active region and an n+-drain region. A peripheral region is provided with a second parallel pn-layer, which has a repetition pitch narrower than the repetition pitch of the first parallel pn-layer. An n−-surface region is formed between the second parallel pn-layer and a first main surface. On the first main surface side of the n−-surface region, a plurality of p-guard ring regions are formed to be separated from each other. A field plate electrode is connected electrically to the outermost p-guard ring region among the p-guard ring regions. A channel stopper electrode is connected electrically to an outermost peripheral p-region of the peripheral region.

摘要翻译： 一种半导体装置，其具有在有源区域和n + - 划分区域之间形成的第一并联pn层。 外围区域设置有第二平行pn层，其具有比第一并联pn层的重复间距窄的重复间距。 在第二平行pn层和第一主表面之间形成n表面区域。 在n面区域的第一主表面侧，形成多个p保护环区域以彼此分离。 场板电极电连接到保护环区域中的最外侧保护环区域。 通道阻挡电极电连接到周边区域的最外周边p区域。