-
11.发明申请公开(公告)号：US20110193853A1
公开(公告)日：2011-08-11
申请号：US12998340
申请日：2009-06-16
CPC分类号： G09G3/3677 , G09G2310/0286 , G11C19/184 , G11C19/28
摘要： There is provided a display device capable of preventing a malfunction and a display defect due to an off-leak from occurring even when a circuit in a shift register is configured utilizing thin film transistors of relatively large off-leaks. In at least one embodiment, each of bistable circuits that constitute the shift register includes: a thin film transistor for increasing a potential of an output terminal based on a first clock; a thin film transistor for decreasing the potential of the output terminal; a thin film transistor for increasing a potential of a range netA connected to a gate terminal of the thin film transistor based on a start signal; thin film transistors for decreasing the potential of the range netA; a capacitor for increasing the potential of a range netB connected to a gate terminal of the thin film transistor; and a thin film transistor for decreasing the potential of the range netB.
摘要翻译： 即使使用相对较大的泄漏的薄膜晶体管构成移位寄存器中的电路，也提供了一种能够防止因泄漏而引起的故障和显示缺陷的显示装置。 在至少一个实施例中，构成移位寄存器的双稳态电路中的每一个包括：用于基于第一时钟增加输出端子的电位的薄膜晶体管; 用于降低输出端子的电位的薄膜晶体管; 薄膜晶体管，用于基于开始信号增加连接到薄膜晶体管的栅极端子的范围netA的电位; 用于降低范围netA的电位的薄膜晶体管; 用于增加连接到薄膜晶体管的栅极端子的范围netB的电位的电容器; 以及用于降低范围netB的电位的薄膜晶体管。
-
公开(公告)号：US06876407B2
公开(公告)日：2005-04-05
申请号：US10400461
申请日：2003-03-28
IPC分类号： G02F1/1335 , G02F1/1365 , H01L49/02 , G02F1/135 , G02F1/136
CPC分类号： G02F1/1365
摘要： A thin film two-terminal element is formed by laminating a protruding portion of a second conductor layer on a first conductor layer via a nonlinear resistor layer. An insulator layer is positioned between the first conductor layer and the second conductor layer except a region to become the thin film two-terminal element. Therefore, the allowance of the relative position of the second conductor layer with respect to the first conductor layer and the nonlinear resistor layer is considerably large as compared with that of prior art, and it is possible to ensure a requisite alignment margin with respect to deformation of the substrate in the production process.
摘要翻译： 通过非线性电阻层将第二导体层的突出部分层叠在第一导体层上形成薄膜二端元件。 除了成为薄膜二端元件的区域之外，绝缘体层位于第一导体层和第二导体层之间。 因此，与现有技术相比，第二导体层相对于第一导体层和非线性电阻层的相对位置的容许度相当大，并且可以确保相对于变形所需的取向余量 的基材在生产过程中。
-
13.发明授权Thin-film two-terminal elements, method of production thereof, liquid crystal display 失效薄膜双端元件，其制造方法，液晶显示器公开(公告)号：US06350557B1
公开(公告)日：2002-02-26
申请号：US09463700
申请日：2000-01-31
申请人： Shigeru Aomori , Yoshiki Nakatani
发明人： Shigeru Aomori , Yoshiki Nakatani
IPC分类号： G02F1136
CPC分类号： H01L45/00 , G02F1/1365
摘要： A thin-film two-terminal element including first metal film functioning as a wiring layer and a first electrode, a first insulating film formed on the first electrode of the first metal film and having a non-linear resistance property, a second metal film formed on the first insulating film and functioning as a second electrode, and a third metal film formed in a wire layer portion of the first metal film and having a smaller stress and a smaller electrical resistance than the first metal film, and a thin-film two-terminal element including, on a resinous substrate as an insulative substrate, a first metal film functioning as a wiring layer and a first electrode, a first insulating film formed on the first electrode of the first metal film and having a non-linear resistance property, a second metal film formed on the first insulating film and functioning as a second electrode, and a second insulating film formed under the second metal film except on a portion thereof which electrically functions with the first electrode via the first insulating film.
摘要翻译： 一种薄膜二端元件，包括用作布线层的第一金属膜和第一电极，形成在第一金属膜的第一电极上并具有非线性电阻特性的第一绝缘膜，形成第二金属膜 在第一绝缘膜上并且起第二电极的作用，以及形成在第一金属膜的导线层部分中并且具有比第一金属膜更小的应力和更小电阻的第三金属膜，以及薄膜二 末端元件包括在作为绝缘基板的树脂基板上的作为布线层的第一金属膜和第一电极，形成在第一金属膜的第一电极上并具有非线性电阻特性的第一绝缘膜 形成在第一绝缘膜上并用作第二电极的第二金属膜，以及形成在第二金属膜之下的第二绝缘膜，除了其一部分之外， 通过第一绝缘膜与第一电极起作用。
-
公开(公告)号：US08653531B2
公开(公告)日：2014-02-18
申请号：US13509367
申请日：2010-07-08
IPC分类号： H01L29/786
CPC分类号： H01L29/78618 , H01L29/66765 , H01L29/78678 , H01L29/78696
摘要： Disclosed is a thin film transistor wherein an ON current is increased and a leak current is reduced. The channel layer 60 of the TFT 10 is formed of a crystalline silicon, and the lower surface of one end of the channel layer 60 is electrically connected to the surface of an n+ silicon layer 40a, and the lower surface of the other end is electrically connected to the surface of an n+ silicon layer 40b. Furthermore, the side surface of said end of the channel layer 60 is electrically connected to a source electrode 50a, and the side surface of the other end is electrically connected to a drain electrode 50b. Thus, a barrier that makes electrons, which act as carriers, not easily transferred is formed on the boundary between the source electrode 50a and the channel layer 60. As a result, the ON current that flows when the TFT 10 is in the ON state can be increased, and the leak current that flows when the TFT is in the OFF state can be reduced.
摘要翻译： 公开了一种薄膜晶体管，其中导通电流增加并且漏电流减小。 TFT10的沟道层60由结晶硅形成，沟道层60的一端的下表面与n +硅层40a的表面电连接，另一端的下表面电气 连接到n +硅层40b的表面。 此外，沟道层60的端部的侧表面电连接到源电极50a，另一端的侧表面电连接到漏电极50b。 因此，在源电极50a和沟道层60之间的边界上形成有作为载流子的电子不容易转移的势垒。其结果是，当TFT10处于导通状态时导通的导通电流 可以降低当TFT处于OFF状态时流过的漏电流。
-
15.发明申请公开(公告)号：US20140028944A1
公开(公告)日：2014-01-30
申请号：US13813839
申请日：2011-07-28
IPC分类号： H01L29/786 , G02F1/1368 , H01L29/66
CPC分类号： H01L29/7869 , G02F1/1368 , H01L27/1225 , H01L27/1255 , H01L27/1288 , H01L29/66742 , H01L29/66969
摘要： A TFT substrate (20a) includes a plurality of pixel electrodes (17a) provided in a matrix, a plurality of TFTs (5) each provided for a corresponding one of the pixel electrodes (17a), and a plurality of auxiliary capacitors (6a) each provided for a corresponding one of the pixel electrodes (17a). Each of the auxiliary capacitors (6a) includes a capacitor line (11b) made of a material identical to that of the gate electrode (11aa) of the TFT (5) and provided in a layer identical to that of the gate electrode (11aa) of the TFT (5), the gate insulating film (12) provided so as to cover the capacitor line (11b), and a corresponding one of the pixel electrodes (17a) provided on the gate insulating film (12) so as to overlap with the capacitor line (11b) and being in conduction with a drain electrode (14ca).
摘要翻译： TFT基板（20a）包括以矩阵形式设置的多个像素电极（17a），分别设置在相应的像素电极（17a）中的多个TFT（5）和多个辅助电容器（6a） 每个设置用于相应的一个像素电极（17a）。 每个辅助电容器（6a）包括由与TFT（5）的栅电极（11aa）相同的材料制成并且设置在与栅电极（11aa）相同的层中的电容器线（11b） 设置为覆盖电容线（11b）的TFT（5），栅极绝缘膜（12）和设置在栅极绝缘膜（12）上的相应的像素电极（17a）重叠 与电容器线（11b）并且与漏电极（14ca）导通。
-
16.发明申请公开(公告)号：US20130214272A1
公开(公告)日：2013-08-22
申请号：US13808375
申请日：2011-07-01
IPC分类号： H01L27/12
CPC分类号： H01L27/1255 , G02F1/136213 , G02F1/13624 , G02F1/1368 , G02F2001/133397 , G02F2001/13606 , G02F2001/136236 , H01L27/1225 , H01L27/1259 , H01L27/1288
摘要： An auxiliary capacitor (6a) includes a capacitor line (11ba), a gate insulating film (12) provided so as to cover the capacitor line (11ba), a semiconductor layer (13b) provided on the gate insulating film (12) so as to overlap with the capacitor line (11b), and a drain electrode (14ba) provided on the semiconductor layer (13b) and connected to a pixel electrode (16a). The semiconductor layer (13b) made of an oxide semiconductor and the pixel electrode (16a) made of an oxide conductor contact each other.
摘要翻译： 辅助电容器（6a）包括电容器线（11ba），设置为覆盖电容器线（11ba）的栅极绝缘膜（12），设置在栅极绝缘膜（12）上的半导体层（13b） 与电容器线（11b）重叠，以及设置在半导体层（13b）上并连接到像素电极（16a）的漏电极（14ba）。 由氧化物半导体构成的半导体层（13b）和由氧化物导体构成的像素电极（16a）彼此接触。
-
17.发明申请公开(公告)号：US20130208207A1
公开(公告)日：2013-08-15
申请号：US13806235
申请日：2011-05-24
IPC分类号： H01L29/04 , G02F1/1368
CPC分类号： H01L29/04 , G02F1/13458 , G02F1/1368 , H01L27/1225 , H01L27/124 , H01L29/7869
摘要： An active matrix substrate (20) includes: a gate electrode (11) provided on an insulating substrate (10a); a gate insulating layer (12) covering the gate electrode (11); an oxide semiconductor layer (13) provided on the gate insulating layer (12); and a protective layer (17) covering the oxide semiconductor layer (13). The active matrix substrate (20) has a display region (D) where an image is displayed and a gate terminal region (Ts) located around the display region (D) and including a gate terminal (26) for connection to an external circuit. The gate terminal (26) includes a terminal line (21) provided on the insulating substrate (10a). The terminal line (26) is made of a conductive material different from a material constituting the oxide semiconductor layer (13).
摘要翻译： 有源矩阵基板（20）包括：设置在绝缘基板（10a）上的栅电极（11）; 覆盖所述栅电极的栅极绝缘层（12）; 设置在栅绝缘层（12）上的氧化物半导体层（13）; 和覆盖氧化物半导体层（13）的保护层（17）。 有源矩阵基板（20）具有显示图像的显示区域（D）和位于显示区域（D）周围的栅极端子区域（Ts），并且包括用于连接到外部电路的栅极端子（26）。 栅极端子（26）包括设置在绝缘基板（10a）上的端子线（21）。 端子线（26）由与构成氧化物半导体层（13）的材料不同的导电材料制成。
-
18.发明授权公开(公告)号：US09196742B2
公开(公告)日：2015-11-24
申请号：US13813839
申请日：2011-07-28
IPC分类号： H01L29/786 , G02F1/1368 , H01L27/12 , H01L29/66
CPC分类号： H01L29/7869 , G02F1/1368 , H01L27/1225 , H01L27/1255 , H01L27/1288 , H01L29/66742 , H01L29/66969
摘要： A TFT substrate (20a) includes a plurality of pixel electrodes (17a) provided in a matrix, a plurality of TFTs (5) each provided for a corresponding one of the pixel electrodes (17a), and a plurality of auxiliary capacitors (6a) each provided for a corresponding one of the pixel electrodes (17a). Each of the auxiliary capacitors (6a) includes a capacitor line (11b) made of a material identical to that of the gate electrode (11aa) of the TFT (5) and provided in a layer identical to that of the gate electrode (11aa) of the TFT (5), the gate insulating film (12) provided so as to cover the capacitor line (11b), and a corresponding one of the pixel electrodes (17a) provided on the gate insulating film (12) so as to overlap with the capacitor line (11b) and being in conduction with a drain electrode (14ca).
摘要翻译： TFT基板（20a）包括以矩阵形式设置的多个像素电极（17a），分别设置在相应的像素电极（17a）中的多个TFT（5）和多个辅助电容器（6a） 每个设置用于相应的一个像素电极（17a）。 每个辅助电容器（6a）包括由与TFT（5）的栅电极（11aa）相同的材料制成并且设置在与栅电极（11aa）相同的层中的电容器线（11b） 设置为覆盖电容线（11b）的TFT（5），栅极绝缘膜（12）和设置在栅极绝缘膜（12）上的相应的像素电极（17a）重叠 与电容器线（11b）并且与漏电极（14ca）导通。
-
公开(公告)号：US08779478B2
公开(公告)日：2014-07-15
申请号：US13701028
申请日：2011-05-23
申请人： Masao Moriguchi , Michiko Takei , Yohsuke Kanzaki , Tsuyoshi Inoue , Tetsuo Fukaya , Yudai Takanishi , Takatsugu Kusumi , Yoshiki Nakatani , Tetsuya Okamoto , Kenji Nakanishi
发明人： Masao Moriguchi , Michiko Takei , Yohsuke Kanzaki , Tsuyoshi Inoue , Tetsuo Fukaya , Yudai Takanishi , Takatsugu Kusumi , Yoshiki Nakatani , Tetsuya Okamoto , Kenji Nakanishi
IPC分类号： H01L29/76 , H01L29/66 , H01L29/786 , H01L29/24
CPC分类号： H01L29/7869 , H01L29/24 , H01L29/66742 , H01L29/66969 , H01L29/78618 , H01L29/78696
摘要： A TFT 20 includes a gate electrode 21, a gate insulating film 22, a semiconductor layer 23, a source electrode 24, a drain electrode 25, etc. The semiconductor layer 23 is comprised of a metal oxide semiconductor (IGZO), and has a source portion 23a that contacts the source electrode 24, a drain electrode 23b that contacts the drain electrode 25, and a channel portion 23c that is located between the source and drain portions 23a, 23b. A reduced region 30 is formed at least in the channel portion 23c of the semiconductor layer 23, and the reduced region 30 has a higher content of a simple substance of a metal such as In than the remaining portion of the semiconductor layer 23.
摘要翻译： TFT20包括栅极电极21，栅极绝缘膜22，半导体层23，源极24，漏极电极25等。半导体层23由金属氧化物半导体（IGZO）构成，具有 与源电极24接触的源部23a，与漏电极25接触的漏电极23b和位于源极部23a，第二漏极23b之间的沟道部23c。 还原区域30至少形成在半导体层23的沟道部分23c中，并且还原区域30具有比半导体层23的其余部分中诸如In的金属的单质更高的含量。
-
公开(公告)号：US08558232B2
公开(公告)日：2013-10-15
申请号：US13387371
申请日：2010-04-21
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L29/04 , H01L29/66757 , H01L29/78609 , H01L29/78675
摘要： The present invention aims at reducing an OFF current in a thin film transistor while maintaining an ON-state current.A TFT (100) includes a glass substrate (101) formed thereon with a source electrode (110) and a drain electrode (112) having their respective upper surfaces formed with n-type silicon layers (120, 121) of microcrystalline silicon. Microcrystalline silicon regions (135, 136) are formed respectively on the n-type silicon layers (120, 121) while an amorphous silicon region (130) is formed on the glass substrate (101), and these are covered by a microcrystalline silicon layer (145). Therefore, ON-state current flows from the drain electrode (112), through the microcrystalline silicon region (135), the microcrystalline silicon layer (145) and the microcrystalline silicon region (136) in this order, and then to the source electrode (110). Also, OFF current is limited by the amorphous silicon region (130).
摘要翻译： 本发明旨在在保持导通状态电流的同时减小薄膜晶体管中的截止电流。 TFT（100）包括形成有源电极（110）的玻璃基板（101）和形成有微晶硅的n型硅层（120,121）的各自上表面的漏电极（112）。 分别在n型硅层（120,121）上形成微晶硅区域（135,136），同时在玻璃基板（101）上形成非晶硅区域（130），并且这些区域被微晶硅层 （145）。 因此，导通状态电流依次通过微晶硅区域（135），微晶硅层（145）和微晶硅区域（136）从漏电极（112）流过，然后流到源电极 110）。 此外，OFF电流受到非晶硅区域（130）的限制。
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.035 秒)
