公开(公告)号：US08385496B1

公开(公告)日：2013-02-26

申请号：US12909744

申请日：2010-10-21

申请人： Allen Chan ,  Wilson Wong ,  Sergey Shumarayev

发明人： Allen Chan ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H04L7/033

摘要： One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.

摘要翻译： 一个实施例涉及一种用于集成电路中的接收机的偏移抵消的方法。 接收机设置为相位检测器偏移消除模式，以便确定相位检测器的偏移消除设置。 偏移消除设置被应用于相位检测器。 然后将接收机设置为接收器 - 驱动器偏移消除模式，以便确定接收器驱​​动器的偏移消除设置。 该偏移消除设置被应用于接收器驱动器。 另一实施例涉及被配置为执行接收机偏移消除的集成电路。 该集成电路包括被配置为接收差分输入信号的接收器驱动器，包括多个锁存器的相位检测器，校准控制器，电压源以及第一和第二对开关。 还公开了其它实施例，方面和特征。

公开(公告)号：US20080225933A1

公开(公告)日：2008-09-18

申请号：US11687052

申请日：2007-03-16

申请人： Allen Chan ,  Wilson Wong ,  Sergey Shumarayev

发明人： Allen Chan ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H04B17/00

CPC分类号： G06F13/385 ,  H03K19/177 ,  H03K19/17744 ,  H04L5/1446

摘要： Automatic rate negotiation logic for a high speed serial interface in a programmable logic device determines whether multiple occurrences of a single-bit transition (i.e., a data transition from “0” to “1” to “0” or from “1” to “0” to “1”) occur within a predetermined time interval on a data channel of a high-speed serial interface. The interval preferably is selected such that multiple occurrences of a single-bit transition mean that the data channel is operating in full-rate mode. The rate negotiation logic may share a phase detector with clock data recovery circuitry in the interface. The phase detector may be a bang-bang phase detector specially adapted to detect single-bit transitions.

摘要翻译： 用于可编程逻辑器件中的高速串行接口的自动速率协商逻辑确定单个位转换的多次出现（即，从“0”到“1”到“0”或从“1”到“1”的数据转换 0“到”1“）发生在高速串行接口的数据信道上的预定时间间隔内。 间隔优选地被选择为使得多次出现单位转换意味着数据信道以全速率模式运行。 速率协商逻辑可以在接口中共享具有时钟数据恢复电路的相位检测器。 相位检测器可以是专门用于检测单位转换的爆发相位检测器。

公开(公告)号：US07602212B1

公开(公告)日：2009-10-13

申请号：US11904003

申请日：2007-09-24

申请人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong

发明人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17732 ,  H03K19/17744

摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes high-speed serial data signal interface channels, some of which include more circuitry that is dedicated to performing various high-speed serial interface functions than others of those channels have. To increase the flexibility with which such circuitry in a more feature-rich channel can be used, routing is provided for selectively allowing a less feature-rich channel to use certain dedicated circuitry of a more feature-rich channel that is not itself using all of its dedicated circuitry.

摘要翻译： 集成电路（例如，可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括高速串行数据信号接口通道，其中一些包括更多专用于执行各种高速串行数据 接口功能比其他那些通道有。 为了增加可以使用更多功能丰富的信道中的这种电路的灵活性，提供路由选择性地允许较不富有特征的信道使用更多功能丰富的信道的某些专用电路，其不是本身使用全部 其专用电路。

公开(公告)号：US08831140B2

公开(公告)日：2014-09-09

申请号：US11687052

申请日：2007-03-16

申请人： Allen Chan ,  Wilson Wong ,  Sergey Shumarayev

发明人： Allen Chan ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H04L27/00 ,  H03K19/177 ,  G06F13/38 ,  H04L5/14

CPC分类号： G06F13/385 ,  H03K19/177 ,  H03K19/17744 ,  H04L5/1446

摘要： Automatic rate negotiation logic for a high speed serial interface in a programmable logic device determines whether multiple occurrences of a single-bit transition (i.e., a data transition from “0” to “1” to “0” or from “1” to “0” to “1”) occur within a predetermined time interval on a data channel of a high-speed serial interface. The interval preferably is selected such that multiple occurrences of a single-bit transition mean that the data channel is operating in full-rate mode. The rate negotiation logic may share a phase detector with clock data recovery circuitry in the interface. The phase detector may be a bang-bang phase detector specially adapted to detect single-bit transitions.

摘要翻译： 用于可编程逻辑器件中的高速串行接口的自动速率协商逻辑确定单个位转换的多次出现（即，从“0”到“1”到“0”或从“1”到“1”的数据转换 0“到”1“）发生在高速串行接口的数据信道上的预定时间间隔内。 间隔优选地被选择为使得多次出现单位转换意味着数据信道以全速率模式运行。 速率协商逻辑可以在接口中共享具有时钟数据恢复电路的相位检测器。 相位检测器可以是专门用于检测单位转换的爆发相位检测器。

公开(公告)号：US08669828B1

公开(公告)日：2014-03-11

申请号：US12909739

申请日：2010-10-21

申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

IPC分类号： H04B3/28

CPC分类号： H01L23/642 ,  H01L2924/0002 ,  H05K1/0231 ,  H01L2924/00

摘要： Integrated circuits with decoupling capacitor circuitry are provided. Decoupling capacitor circuitry may include multiple arrays of decoupling capacitors. Each decoupling capacitor array may have a corresponding decoupling capacitor monitoring circuit that is associated with that decoupling capacitor array. Each decoupling capacitor monitoring circuit may include a resistor and switching circuitry. Each decoupling capacitor monitoring circuit may be coupled to a comparator and control circuitry. During testing, the control circuitry may configure each decoupling capacitor array for leakage current testing one at a time. If a decoupling capacitor array is determined to exhibit excessive leakage currents, that decoupling capacitor array will be marked as defective and will be disabled from use. If the decoupling capacitor array is determined to exhibit tolerable leakage currents, that decoupling capacitor array will be enable for use to help reduce power supply noise.

摘要翻译： 提供具有去耦电容电路的集成电路。 去耦电容器电路可以包括多个去耦电容器阵列。 每个去耦电容器阵列可以具有与该去耦电容器阵列相关联的相应的去耦电容器监控电路。 每个去耦电容器监控电路可以包括电阻器和开关电路。 每个去耦电容器监控电路可以耦合到比较器和控制电路。 在测试期间，控制电路可以配置每个去耦电容器阵列以便一次一个地进行漏电流测试。 如果解耦电容器阵列被确定为表现出过多的漏电流，则该去耦电容阵列将被标记为有缺陷的并且将被禁止使用。 如果解耦电容器阵列被确定为表现出可容忍的漏电流，则该去耦电容器阵列将被用于帮助减少电源噪声。

公开(公告)号：US08175143B1

公开(公告)日：2012-05-08

申请号：US12037284

申请日：2008-02-26

申请人： Wilson Wong ,  Tin H. Lai ,  Allen Chan ,  Tim Tri Hoang ,  Sergey Shumarayev

发明人： Wilson Wong ,  Tin H. Lai ,  Allen Chan ,  Tim Tri Hoang ,  Sergey Shumarayev

IPC分类号： H03H7/30

CPC分类号： H04L25/03057 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03745 ,  H04L2025/03783

摘要： A method, and circuitry, for choosing the correct equalization curve in adaptive equalization uses a feedback loop in which the incoming high-speed serial data are digitized and deserialized for use in the remainder of the device, and also are used by an adaptive state machine to both extract the reference levels for digitization and to control the equalization curve. Detection of the reference level and selection of the equalization curve may be performed at a different rates to avoid interfering with one another. The state machine preferably is programmable. This is useful in any device, but is particularly well-suited for a programmable device, such as a PLD or other programmable integrated circuit device, where conditions may vary according a user logic design.

摘要翻译： 用于在自适应均衡中选择正确的均衡曲线的方法和电路使用反馈回路，其中输入的高速串行数据被数字化和反序列化以用于设备的其余部分，并且还被自适应状态机 以提取用于数字化的参考电平并控制均衡曲线。 参考电平的检测和均衡曲线的选择可以以不同的速率进行，以避免彼此干扰。 状态机优选是可编程的。 这在任何设备中是有用的，但是特别适用于诸如PLD或其他可编程集成电路设备的可编程设备，其中条件可以根据用户逻辑设计而变化。

公开(公告)号：US07924184B1

公开(公告)日：2011-04-12

申请号：US11904008

申请日：2007-09-24

申请人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong

发明人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong

IPC分类号： H03M9/00

CPC分类号： H03K19/1732

摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and a channel of high-speed serial data signal interface (e.g., transceiver) circuitry. To facilitate enabling the integrated circuit to support any of many possible different high-speed serial communication protocols, the channel is hard-wired to include a parallel data bus of fixed width for exchanging parallel data with the programmable circuitry. Regardless of the protocol being implemented, the full width of this bus is always used. A portion of the programmable circuitry is programmed to convert data between the block width and a group width, which can be different from the block width and which is used for the data elsewhere in the integrated circuit.

摘要翻译： 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和高速串行数据信号接口（例如，收发器）电路的通道。 为了使集成电路能够支持许多可能的不同高速串行通信协议中的任何一种，该信道被硬接线以包括用于与可编程电路交换并行数据的固定宽度的并行数据总线。 无论正在执行协议，始终使用该总线的全宽。 可编程电路的一部分被编程为在块宽度和组宽度之间转换数据，其可以与块宽度不同，并且用于集成电路中其他地方的数据。

公开(公告)号：US20100090774A1

公开(公告)日：2010-04-15

申请号：US12277810

申请日：2008-11-25

申请人： Sergey Shumarayev ,  Wilson Wong ,  Allen Chan ,  Ali Atesoglu

发明人： Sergey Shumarayev ,  Wilson Wong ,  Allen Chan ,  Ali Atesoglu

IPC分类号： H03B5/18

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/011

摘要： An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.

摘要翻译： 振荡器电路包括通过第一导电层中的路由导体交叉耦合的晶体管。 振荡器电路还包括第二导电层中的变容二极管，电容器和选项导体。 选项导体形成晶体管之一和电容器或变容二极管之间的连接的至少一部分。

公开(公告)号：US08035453B1

公开(公告)日：2011-10-11

申请号：US12577568

申请日：2009-10-12

申请人： Wilson Wong ,  Allen Chan ,  Simardeep Maangat ,  Sergey Shumarayev

发明人： Wilson Wong ,  Allen Chan ,  Simardeep Maangat ,  Sergey Shumarayev

IPC分类号： H03K3/03 ,  H03L1/00 ,  H03L7/099

CPC分类号： H03K3/0322 ,  H03L7/0995 ,  H03L2207/06

摘要： An oscillator circuit includes differential variable delay circuits coupled together to form a ring oscillator. Each of the differential variable delay circuits has first and second inputs and first, second, third, and fourth transistors. A constant supply voltage is provided to sources of the first and the second transistors in each of the differential variable delay circuits. A variable supply voltage is provided to sources of the third and the fourth transistors in each of the differential variable delay circuits. Gates of the first and the third transistors are coupled to the first input. Gates of the second and the fourth transistors are coupled to the second input. The oscillator circuit generates a periodic output signal having a frequency that varies based on changes in the variable supply voltage.

摘要翻译： 振荡器电路包括耦合在一起以形成环形振荡器的差分可变延迟电路。 每个差分可变延迟电路具有第一和第二输入以及第一，第二，第三和第四晶体管。 在每个差分可变延迟电路中，向第一和第二晶体管的源极提供恒定的电源电压。 可变电源电压被提供给每个差分可变延迟电路中的第三和第四晶体管的源极。 第一和第三晶体管的栅极耦合到第一输入端。 第二和第四晶体管的栅极耦合到第二输入端。 振荡器电路产生具有基于可变电源电压的变化而变化的频率的周期性输出信号。

公开(公告)号：US20100109675A1

公开(公告)日：2010-05-06

申请号：US12263290

申请日：2008-10-31

申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

IPC分类号： G01R31/02

CPC分类号： G01R31/3167

摘要： An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.

摘要翻译： 提出了一种能够监视模拟模块内的模拟电压的集成电路。 集成电路具有模拟测试复用器（多路复用器），其输入端连接到模拟模块内的感兴趣的模拟电压。 模拟测试复用器将选定的模拟电压从模拟模块引导到模拟测试复用器的输出。 集成电路还包括模拟监视状态机，其向模拟测试多路复用器提供选择位，使得能够随机访问模拟块内的模拟电压。 集成电路还包括用于将来自模拟测试多路复用器的所选模拟电压转换为数字表示的模数转换器。