公开(公告)号：US07702838B2

公开(公告)日：2010-04-20

申请号：US10844531

申请日：2004-05-13

申请人： Emory D. Keller

发明人： Emory D. Keller

IPC分类号： G06F13/14

CPC分类号： G06F13/423

摘要： A configuration space bus includes a configuration space on a primary interface and an extension or secondary interface in communication with a configuration space of the primary interface. When the primary interface receives a transaction request which it does not recognize, the transaction request is passed to the secondary interface for processing. The primary bus then waits for a response from the secondary bus. If the primary interface receives a transaction request which it does recognize, that transaction request is processed by the primary bus. The extension interface allows the primary bus to receive and process industry standard specification defined commands as well as forward commands defined by a user to the extension bus for processing. Multiple buses may be cascaded to form a primary extension interface, a secondary interface, a third interface, etc. A transaction request is passed down through such a chain of interfaces until an interface recognizes and processes it.

摘要翻译： 配置空间总线包括主接口上的配置空间和与主接口的配置空间通信的分机或辅助接口。 当主界面接收到无法识别的事务请求时，将事务请求传递到辅助接口进行处理。 然后，主要总线等待辅助总线的响应。 如果主界面接收到它确认的事务请求，该事务请求将被主总线处理。 扩展接口允许主总线接收和处理行业标准规范定义的命令以及由用户定义的转发命令到扩展总线进行处理。 多个总线可以级联以形成主扩展接口，辅助接口，第三接口等。事务请求通过这样的接口链传递，直到接口识别和处理它。

公开(公告)号：US07689887B2

公开(公告)日：2010-03-30

申请号：US11962781

申请日：2007-12-21

申请人： Kevin W. Gorman ,  Emory D. Keller ,  Michael R. Ouellette

发明人： Kevin W. Gorman ,  Emory D. Keller ,  Michael R. Ouellette

IPC分类号： G06F11/00 ,  G06F13/24 ,  G01R31/28 ,  G01R31/00 ,  G01R31/02

CPC分类号： G11C29/14 ,  G01K3/005 ,  G11C29/12 ,  G11C2029/5002

摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodied in a machine readable medium are provided. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.

摘要翻译： 内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关联的BIST测试操作，以及包括BIST的设计结构 提供了体现在机器可读介质中的状态机。 热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。 响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。 这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。

公开(公告)号：US20090161722A1

公开(公告)日：2009-06-25

申请号：US11962781

申请日：2007-12-21

申请人： Kevin W. Gorman ,  Emory D. Keller ,  Michael R. Ouellette

发明人： Kevin W. Gorman ,  Emory D. Keller ,  Michael R. Ouellette

IPC分类号： G01K13/00

CPC分类号： G11C29/14 ,  G01K3/005 ,  G11C29/12 ,  G11C2029/5002

摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodied in a machine readable medium are provided. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.

摘要翻译： 内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关联的BIST测试操作，以及包括BIST的设计结构 提供了体现在机器可读介质中的状态机。 热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。 响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。 这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。

公开(公告)号：US20090052609A1

公开(公告)日：2009-02-26

申请号：US11841125

申请日：2007-08-20

申请人： Valerie Hornbeck Chickanosky ,  Kevin William Gorman ,  Emory D. Keller ,  Michael Richard Ouellette

发明人： Valerie Hornbeck Chickanosky ,  Kevin William Gorman ,  Emory D. Keller ,  Michael Richard Ouellette

IPC分类号： G01F15/06

CPC分类号： G01R31/31724 ,  G01R31/31721

摘要： A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.

摘要翻译： 一种包括用于启用枚举操作的控制器的系统。 枚举操作由系统中的控制器（110）和逻辑元件（120）执行，使得系统中的每个逻辑元件分配自身唯一的标识符。 然后，每个逻辑元件可以被另一个源控制，或者具有与系统中的其它逻辑元件通信的手段。 独特的标识符可以实现更大的系统灵活性，从而降低成本并提高效率。

公开(公告)号：US20080222464A1

公开(公告)日：2008-09-11

申请号：US12126452

申请日：2008-05-23

申请人： Kevin W. Gorman ,  Emory D. Keller ,  Michael R. Ouellette ,  Donald L. Wheater

发明人： Kevin W. Gorman ,  Emory D. Keller ,  Michael R. Ouellette ,  Donald L. Wheater

IPC分类号： G11C29/12 ,  G06F11/27

CPC分类号： G11C29/40 ,  G01R31/31703 ,  G01R31/31704 ,  G11C2029/3202

摘要： A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.

摘要翻译： 公开了一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法的设计结构。 特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。 测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。 通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器 将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。