公开(公告)号：US20050079697A1

公开(公告)日：2005-04-14

申请号：US10666025

申请日：2003-09-17

Applicant: Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip Campbell ,  Gurtej Sandhu

Inventor： Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip Campbell ,  Gurtej Sandhu

IPC: C23C16/42 ,  H01L21/285 ,  H01L21/44

CPC classification number: H01L21/28518 ,  C23C16/42 ,  H01L21/28556

Abstract: Chemical vapor deposition methods of forming titanium silicide including layers on substrates are disclosed. TiCl4 and at least one silane are first fed to the chamber at or above a first volumetric ratio of TiCl4 to silane for a first period of time. The ratio is sufficiently high to avoid measurable deposition of titanium silicide on the substrate. Alternately, no measurable silane is fed to the chamber for a first period of time. Regardless, after the first period, TiCl4 and at least one silane are fed to the chamber at or below a second volumetric ratio of TiCl4 to silane for a second period of time. If at least one silane was fed during the first period of time, the second volumetric ratio is lower than the first volumetric ratio. Regardless, the second feeding is effective to plasma enhance chemical vapor deposit a titanium silicide including layer on the substrate.

Abstract translation: 公开了在衬底上形成包括层的硅化钛的化学气相沉积方法。 首先将TiCl 4和至少一种硅烷以等于或高于TiCl 4与硅烷的第一体积比在第一时间段内进料至室。 该比例足够高以避免钛硅化物在衬底上的可测量沉积。 或者，在第一时间段内没有可测量的硅烷进料到室中。 无论如何，在第一阶段之后，将TiCl 4和至少一种硅烷以等于或低于第二体积比的TiCl 4与硅烷进料至室中第二时间段。 如果在第一时间段内进料至少一种硅烷，则第二体积比率低于第一体积比。 无论如何，第二次进料对于等离子体有效地提高了化学气相沉积在基底上的包含硅的硅化钛。

公开(公告)号：US06858904B2

公开(公告)日：2005-02-22

申请号：US09944903

申请日：2001-08-30

Applicant: Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

Inventor： Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

IPC: H01L21/285 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/45 ,  H01L29/76 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76868 ,  H01L21/76877 ,  H01L29/456

Abstract: A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening and directly contacts an upper surface of the substrate. Silicon-doping of CVD titanium, from the addition of SiH4 during deposition, reduces consumption of substrate silicon during the subsequent silicidation reaction in which the titanium reacts with silicon to form a titanium silicide layer that provides low resistance electrical contacts between the junction region and the silicon substrate. The contact structure further comprises a titanium nitride contact fill that is deposited in the contact opening and fills substantially the entire contact opening.

Abstract translation: 形成在硅衬底的接合区域上的高纵横比接触结构包括散布有硅化钛层的钛，其沉积在接触开口中并直接接触衬底的上表面。 在沉积期间从添加SiH 4中掺杂CVD钛的Si掺杂减少了在随后的硅化反应期间底物硅的消耗，其中钛与硅反应形成硅化钛层，其在接合区域和接合区域之间提供低电阻电接触 硅衬底。 接触结构还包括氮化钛接触填料，其沉积在接触开口中并基本上填充整个接触开口。

公开(公告)号：US20050032361A1

公开(公告)日：2005-02-10

申请号：US10931854

申请日：2004-09-01

Applicant: Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

Inventor： Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

IPC: H01L21/285 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/45 ,  H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76868 ,  H01L21/76877 ,  H01L29/456

Abstract: A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening and directly contacts an upper surface of the substrate. Silicon-doping of CVD titanium, from the addition of SiH4 during deposition, reduces consumption of substrate silicon during the subsequent silicidation reaction in which the titanium reacts with silicon to form a titanium silicide layer that provides low resistance electrical contacts between the junction region and the silicon substrate. The contact structure further comprises a titanium nitride contact fill that is deposited in the contact opening and fills substantially the entire contact opening.

公开(公告)号：US06790114B2

公开(公告)日：2004-09-14

申请号：US10109847

申请日：2002-04-01

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J924

CPC classification number: H01J9/185 ,  H01J31/127 ,  H01J2201/319

Abstract: Field emitter display (FED) assemblies and methods of forming field emitter display (FED) assemblies are described. In one embodiment, a substrate is provided having a column line formed and supported thereby. A plurality of field emitter tip regions are formed and disposed in operable proximity to the column line. At least some of the regions define different pixels of the display. A continuous resistor is interposed between the column line and at least two different pixels. In another embodiment, a column line is formed and supported by a substrate. A plurality of field emitter tip regions are formed and disposed in operable proximity to the column line. The regions define different pixels of the display. A single current-limiting resistor is operably coupled with the column line and at least two different pixels. In yet another embodiment, a series of column lines are formed over a substrate. A series of field emitter tip regions are formed and arranged into discrete pixels which are disposed in operable proximity to individual respective column lines. A series of resistor strips is formed and supported by the substrate. The resistor strips individually underlie respective individual series of field emitter tip regions. The individual resistor strips operably connect respective column lines and field emitter tip regions. At least one of the resistor strips operably connects its associated column line and at least two different discrete pixels. Other embodiments are described.

Abstract translation: 描述了场发射器显示（FED）组件和形成场发射器显示（FED）组件的方法。 在一个实施例中，提供具有形成并由其支撑的列线的基板。 多个场发射极尖端区域形成并布置成可操作地接近列线。 至少一些区域定义显示器的不同像素。 在列线和至少两个不同的像素之间插入连续电阻。 在另一个实施例中，柱线由衬底形成并支撑。 多个场发射极尖端区域形成并布置成可操作地接近列线。 这些区域定义显示器的不同像素。 单个限流电阻器与列线和至少两个不同的像素可操作地耦合。 在另一个实施例中，在衬底上形成一系列列线。 一系列场发射器尖端区域形成并布置成离散的像素，这些离散像素设置成可操作地接近各个相应的列线。 一系列电阻条由衬底形成并支撑。 电阻带分别位于各个系列的场发射器尖端区域的下面。 各个电阻条可操作地连接相应的列线和场发射极尖端区域。 电阻条中的至少一个可操作地连接其相关联的列线和至少两个不同的离散像素。 描述其他实施例。

公开(公告)号：US06552478B2

公开(公告)日：2003-04-22

申请号：US09944486

申请日：2001-08-30

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J102

CPC classification number: H01J9/025

Abstract: Each pixel of a field emission device includes a resistor with at least one emitter tip thereover and at least one substantially vertically oriented conductive element positioned adjacent the resistor. In a field emission array, a conductive element may contact each resistor of a line of pixels. A method for fabricating the field emission array includes forming a plurality of substantially parallel conductive lines, depositing at least one layer of semiconductive or conductive material over and laterally adjacent each conductive line, and forming a hard mask in recesses of the surface of the uppermost material layer. The underlying material layer or layers are patterned through the hard mask, exposing substantially longitudinal center portions of the conductive lines. The remaining semiconductive or conductive material is patterned to form the emitter tips and resistors. At least the substantially central longitudinal portions of the conductive traces are removed to form the conductive elements.

Abstract translation: 场发射器件的每个像素包括具有至少一个发射极尖端的电阻器以及邻近电阻器定位的至少一个基本垂直定向的导电元件。 在场发射阵列中，导电元件可以接触像素线的每个电阻器。 一种用于制造场致发射阵列的方法包括形成多个基本上平行的导电线，在每个导电线之上和之后沉积至少一层半导体或导电材料，并在最上面的材料的表面的凹槽中形成硬掩模 层。 通过硬掩模对下面的材料层或图案进行图案化，暴露导电线的基本上纵向的中心部分。 剩余的半导体或导电材料被图案化以形成发射极尖端和电阻器。 导电迹线的至少基本上中心的纵向部分被去除以形成导电元件。

公开(公告)号：US06461211B2

公开(公告)日：2002-10-08

申请号：US09888125

申请日：2001-06-22

Applicant: Kanwal K. Raina ,  Ammar Derraa

Inventor： Kanwal K. Raina ,  Ammar Derraa

IPC: H01J924

CPC classification number: H01J1/3044 ,  H01J9/025

Abstract: In one aspect, an electron emission device comprises a substrate, and a first layer supported by the substrate. The first layer comprises a conductive material. The electron emission display device further comprises an electron emission tip electrically connected with the first layer, and a second layer electrically disposed between the first layer and the electron emission tip. The second layer comprises microcrystalline silicon. In another aspect, the invention encompasses a method of forming an electron emission device. A substrate is provided, and a conductive layer is formed over the substrate. A microcrystalline-silicon-containing layer is formed over the conductive layer, and a resistor layer is formed over the microcrystalline-silicon-containing layer. An emitter tip is formed over the resistor layer. In yet other aspects, the invention encompasses field emission display devices, and methods of forming field emission display devices.

Abstract translation: 一方面，电子发射器件包括衬底和由衬底支撑的第一层。 第一层包括导电材料。 电子发射显示装置还包括与第一层电连接的电子发射尖端，以及电气设置在第一层和电子发射尖端之间的第二层。 第二层包括微晶硅。 另一方面，本发明包括形成电子发射装置的方法。 提供衬底，并且在衬底上形成导电层。 在导电层上形成微晶硅层，在微晶硅层上形成电阻层。 发射极尖端形成在电阻层上。 在其它方面，本发明包括场发射显示装置，以及形成场致发射显示装置的方法。

公开(公告)号：US06443788B2

公开(公告)日：2002-09-03

申请号：US09939888

申请日：2001-08-27

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J900

CPC classification number: H01J9/025

Abstract: A method for fabricating row lines and pixel openings of a field emission array that employs only two masks. A first mask is disposed over electrically conductive material and semiconductive material and includes apertures that are alignable between rows of pixels of the field emission array. Row lines of the field emission array are defined through the first mask. A passivation layer is then disposed over at least selected portions of the field emission array. A second mask, including apertures alignable over the pixel regions of the field emission array, is disposed over the passivation layer. The second mask is used in defining openings through the passivation layer and over the pixel regions of the field emission array. Conductive material exposed through the apertures of the second mask may also be removed to expose the underlying semiconductive grid and to further define the pixel openings.

Abstract translation: 一种用于制造仅使用两个掩模的场致发射阵列的行线和像素开口的方法。 第一掩模设置在导电材料和半导体材料之上，并且包括可以在场发射阵列的像素行之间对准的孔。 通过第一个掩模定义场发射阵列的行线。 然后将钝化层设置在场致发射阵列的至少选定部分上。 包括在场发射阵列的像素区域上对准的孔的第二掩模设置在钝化层上。 第二掩模用于限定穿过钝化层的开口和场致发射阵列的像素区域。 通过第二掩模的孔暴露的导电材料也可以被去除以暴露下面的半导电栅格并进一步限定像素开口。

公开(公告)号：US06417627B1

公开(公告)日：2002-07-09

申请号：US09243929

申请日：1999-02-03

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: G09G310

CPC classification number: H01J31/127

Abstract: A matrix-addressable device includes a number of metal column lines having a number of windows underlying locations of intersection where a number of metal row lines overlap or cross the column lines. Each of the windows has a length that is greater than the nominal width of the row line crossing the column line. A layer of a doped semiconductor overlaps each of the windows to electrically couple a number of emitters formed on the doped semiconductor to the column lines. Each of the metal row lines may include a number of windows positioned at the locations where the row and column lines overlap. Each of the windows has a length greater than a nominal width of the column line that the window overlays. A doped semiconductor layer covers each of the windows and is electrically coupled thereto. A number of apertures formed in the doped semiconductor layer aligned with the emitters to form an extraction grid. A layer of dielectric material may separate the column lines from the row lines.

Abstract translation: 矩阵寻址装置包括多个金属列线，其具有多个金属列线重叠或跨越列线的交叉点的下面的多个窗口。 每个窗口的长度大于穿过列线的行线的标称宽度。 掺杂半导体层与每个窗口重叠，以将形成在掺杂半导体上的多个发射极电耦合到列线。 每个金属行线可以包括位于行和列线重叠的位置处的多个窗口。 每个窗口的长度大于窗口叠加的列线的标称宽度。 掺杂半导体层覆盖每个窗口并且电耦合到其上。 形成在掺杂半导体层中的多个孔与发射体对准以形成提取栅格。 介电材料层可以将列线与行线分开。

公开(公告)号：US06387718B2

公开(公告)日：2002-05-14

申请号：US09942148

申请日：2001-08-29

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L2100

CPC classification number: H01J9/025

Abstract: A method for fabricating field emission arrays employs a single mask to define emitter tips, their corresponding resistors, and, optionally, conductive lines. One or more material layers from which the emitter tips and resistors will be defined are formed over and laterally adjacent substantially parallel conductive lines. The exposed surface of the layer or layers of emitter tip and resistor material or materials may be planarized. The emitter tips and underlying resistors are then defined. Substantially longitudinal center portions of the conductive lines may be exposed between adjacent lines of emitter tips, with at least a lateral edge portion of each conductive line being shielded by material that remains following the formation of the emitter tips and resistors. The exposed portions of the conductive lines may be removed in order to define conductive traces. Field emission arrays and display devices fabricated by such methods are also disclosed.

Abstract translation: 用于制造场发射阵列的方法使用单个掩模来限定发射极尖端，它们相应的电阻器，以及可选地导电线路。 将限定发射极尖端和电阻器的一个或多个材料层形成在基本上平行的导线上方和侧向相邻。 发射极尖端和电阻器材料或材料的层的暴露表面可以被平坦化。 然后定义发射极尖端和底层电阻。 导线的基本上纵向的中心部分可以在相邻的发射极尖端之间露出，每个导线的至少一个侧边缘部分被形成发射极尖端和电阻器后的材料屏蔽。 可以去除导线的暴露部分以便限定导电迹线。 还公开了通过这种方法制造的场发射阵列和显示装置。

公开(公告)号：US06333593B1

公开(公告)日：2001-12-25

申请号：US09373323

申请日：1999-08-12

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J102

CPC classification number: H01J9/025

Abstract: A method of fabricating field emission arrays which employs a single mask to define emitter tips and their corresponding resistors. Column lines may also be defined without requiring the use of an additional mask. The method includes disposing substantially mutually parallel conductive lines onto a substrate of the field emission array. The conductive lines may be patterned from a layer of conductive material or selectively deposited onto the substrate. One or more material layers, from which the emitter tips and resistors will be defined, are disposed onto the conductive lines and the regions of substrate exposed between adjacent conductive lines. The exposed surface of the layer or layers of emitter tip and resistor material or materials may be planarized. A mask is disposed over the substantially planar surface. The emitter tips and resistors are defined through the mask and substantially longitudinal center portions of the conductive lines exposed through the layer or layers of emitter tip and resistor material or materials. The substantially longitudinal center portions of the conductive lines may be removed in order to define column lines and to electrically isolate adjacent column lines from one another. A field emission array that has been fabricated in accordance with the method of the present invention is also within the scope of the present invention. Such a field emission array may include a substrate including resistors protruding therefrom, column lines laterally adjacent the resistors, and one or more emitter tips disposed substantially above each of the resistors.

Abstract translation: 一种制造场发射阵列的方法，其使用单个掩模来限定发射极尖端及其对应的电阻器。 也可以定义列线，而不需要使用额外的掩模。 该方法包括将基本相互平行的导线设置在场发射阵列的衬底上。 导电线可以从导电材料层图案化或选择性地沉积到衬底上。 将限定发射极尖端和电阻器的一个或多个材料层设置在导线上并且暴露在相邻导线之间的衬底区域。 发射极尖端和电阻器材料或材料的层的暴露表面可以被平坦化。 掩模设置在基本平坦的表面上。 发射极尖端和电阻器通过掩模和通过发射极尖端和电阻器材料或材料的层暴露的导线的基本纵向中心部分来限定。 可以去除导线的基本上纵向的中心部分以便限定列线并且使彼此相邻的列线电隔离。 根据本发明的方法制造的场致发射阵列也在本发明的范围内。 这样的场发射阵列可以包括包括从其突出的电阻器的衬底，与电阻器横向相邻的列线，以及基本上设置在每个电阻器上方的一个或多个发射极尖端。