公开(公告)号：US06963206B2

公开(公告)日：2005-11-08

申请号：US10946558

申请日：2004-09-21

申请人： Deepak A. Ramappa

发明人： Deepak A. Ramappa

IPC分类号： G01N23/06 ,  G01N27/60

CPC分类号： G01N23/06

摘要： The present invention provides a system and method for evaluating gate oxide integrity in a semiconductor wafer. The system may include: a semiconductor wafer; a layer of gate oxide on the semiconductor wafer; a layer of polysilicon on the gate oxide; an electron beam microscope with adjustable energy levels, wherein the electron beam is directed at the semiconductor wafer; an electron beam inspection tool used to detect passive voltage contrasts within the gate oxide layer. The system may also include a measuring tool for measuring an electrical current level of the semiconductor substrate. The system may also include an electrical ground connected to the semiconductor wafer. The system may also include the energy levels vary from about 600 eV to 5000 eV.

摘要翻译： 本发明提供了一种用于评估半导体晶片中的栅极氧化物完整性的系统和方法。 该系统可以包括：半导体晶片; 半导体晶片上的栅极氧化物层; 栅氧化层上的多晶硅层; 具有可调节能级的电子束显微镜，其中电子束被引导到半导体晶片; 用于检测栅极氧化物层内的被动电压对比度的电子束检查工具。 该系统还可以包括用于测量半导体衬底的电流水平的测量工具。 该系统还可以包括连接到半导体晶片的电接地。 该系统还可以包括能量水平从约600eV变化到5000eV。

公开(公告)号：US06812050B1

公开(公告)日：2004-11-02

申请号：US10463022

申请日：2003-06-13

申请人： Deepak A. Ramappa

发明人： Deepak A. Ramappa

IPC分类号： H01L2100

CPC分类号： G01N23/06

摘要： The present invention provides a system and method for evaluating gate oxide integrity in a semiconductor wafer. The system may include: a semiconductor wafer; a layer of gate oxide on the semiconductor wafer; a layer of polysilicon on the gate oxide; an electron beam microscope with adjustable energy levels, wherein the electron beam is directed at the semiconductor wafer; an electron beam inspection tool used to detect passive voltage contrasts within the gate oxide layer. The system may also include a measuring tool for measuring an electrical current level of the semiconductor substrate. The system may also include an electrical ground connected to the semiconductor wafer. The system may also include the energy levels vary from about 600 eV to 5000 eV.

摘要翻译： 本发明提供了一种用于评估半导体晶片中的栅极氧化物完整性的系统和方法。 该系统可以包括：半导体晶片; 半导体晶片上的栅极氧化物层; 栅氧化层上的多晶硅层; 具有可调节能级的电子束显微镜，其中电子束被引导到半导体晶片; 用于检测栅极氧化物层内的被动电压对比度的电子束检查工具。 该系统还可以包括用于测量半导体衬底的电流水平的测量工具。 该系统还可以包括连接到半导体晶片的电接地。 该系统还可以包括能量水平从约600eV变化到5000eV。

公开(公告)号：US06607927B2

公开(公告)日：2003-08-19

申请号：US09968243

申请日：2001-09-28

申请人： Deepak A. Ramappa ,  Damon Keith DeBusk

发明人： Deepak A. Ramappa ,  Damon Keith DeBusk

IPC分类号： H01L2166

CPC分类号： H01L22/14

摘要： A method for determining copper contamination on a semiconductor wafer is disclosed. The minority carrier diffusion length is measured, then the wafer is activated by the application of optical or thermal energy. Likely the wafer is also contaminated with iron and thus it is necessary to separate the diffusion length effects caused by the iron from those caused by the copper, that is, both copper and iron contaminants cause a reduction in the minority carrier diffusion length. The applied energy causes the iron-boron pairs to dissociate and also causes the copper to form a metastable copper silicide state. After about 24 to 36 hours, the iron-boron pairs reform and therefore the iron contaminants no longer influence the diffusion length. At this point the diffusion length is measured again, which values are due solely to the copper contamination, since the copper remains in the silicide state. The copper contamination can be determined from the measured diffusion length values.

摘要翻译： 公开了一种用于确定半导体晶片上铜污染的方法。 测量少数载流子扩散长度，然后通过应用光学或热能激活晶片。 晶片也可能被铁污染，因此有必要将由铁引起的扩散长度影响与由铜引起的扩散长度影响分开，即铜和铁污染物会导致少数载流子扩散长度的减小。 所施加的能量导致铁 - 硼对解离，并且还导致铜形成亚稳态硅化铜状态。 约24至36小时后，铁 - 硼对改性，因此铁污染物不再影响扩散长度。 此时再次测量扩散长度，由于铜保持在硅化物状态，所以这些值仅归因于铜污染。 可以从测量的扩散长度值确定铜污染。

公开(公告)号：US06573183B2

公开(公告)日：2003-06-03

申请号：US09965739

申请日：2001-09-28

申请人： Sailesh Mansinh Merchant ,  Minseok Oh ,  Deepak A. Ramappa

发明人： Sailesh Mansinh Merchant ,  Minseok Oh ,  Deepak A. Ramappa

IPC分类号： H01L21449

CPC分类号： C25D17/001 ,  C25D5/20 ,  H01L21/2885 ,  Y10S438/913

摘要： A method and apparatus for the electroplating deposition of a metal onto a semiconductor wafer surface (29), including vibrationally scrubbing the wafer surface (29) during an electroplating process. At least one transducer (32) is mounted to a wall (33) of an electroplating tool chamber (22). The transducer (32) intermittently delivers sonic energy pulses lasting for one to two seconds to the electroplating solution during the electroplating process.

摘要翻译： 一种用于将金属电镀沉积到半导体晶片表面（29）上的方法和装置，包括在电镀过程中振动洗涤晶片表面（29）。 至少一个换能器（32）安装到电镀工具室（22）的壁（33）上。 在电镀过程中，换能器（32）间歇地传送持续1至2秒的电能脉冲到电镀溶液。

公开(公告)号：US07910477B2

公开(公告)日：2011-03-22

申请号：US11965972

申请日：2007-12-28

申请人： Jeannette Michelle Jacques ,  Deepak A. Ramappa

发明人： Jeannette Michelle Jacques ,  Deepak A. Ramappa

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/76814

摘要： Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles.

摘要翻译： 提供了形成双镶嵌互连结构的方法。 该方法包括灰化操作，其包括第一灰分操作和第二溢出操作。 灰蚀操作在刻蚀停止层之前进行。 该操作从在形成互连结构期间形成的空腔中去除残留物，并且便于更好的CD控制而不改变空腔轮廓。

公开(公告)号：US07312151B2

公开(公告)日：2007-12-25

申请号：US11334181

申请日：2006-01-17

申请人： Aaron Frank ,  David Gonzalez ,  John DeGenova ,  Srinavas Raghavan ,  Deepak A. Ramappa

发明人： Aaron Frank ,  David Gonzalez ,  John DeGenova ,  Srinavas Raghavan ,  Deepak A. Ramappa

IPC分类号： H01L21/44

CPC分类号： H01L21/76856 ,  B08B7/0057 ,  C25D5/34 ,  H01L21/321 ,  H01L21/67028 ,  H01L21/67115 ,  H01L21/76862 ,  H01L21/76873

摘要： The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate (206). The present invention provides a housing (204) to enclose the semiconductor substrate within. An ultraviolet radiation source (210) is disposed within the housing. A treatment medium (208) is also provided within the housing. The semiconductor substrate is enclosed within the housing and exposed to the treatment medium. The ultraviolet radiation source exposes the semiconductor substrate to ultraviolet radiation, desorbing the contaminants from the seed layer.

摘要翻译： 本发明提供了一种从已沉积在半导体衬底（206）上的铜籽晶层去除有机污染物（216）的系统。 本发明提供一种将半导体衬底包围的壳体（204）。 紫外线辐射源（210）设置在壳体内。 处理介质（208）也设置在壳体内。 将半导体衬底封装在壳体内并暴露于处理介质。 紫外线辐射源将半​​导体衬底暴露于紫外线辐射，从种子层解吸污染物。

公开(公告)号：US06869873B2

公开(公告)日：2005-03-22

申请号：US10609889

申请日：2003-06-30

申请人： Robert Wayne Bradshaw ,  Daniele Gilkes ,  Sailesh Mansinh Merchant ,  Deepak A. Ramappa ,  Kurt George Steiner

发明人： Robert Wayne Bradshaw ,  Daniele Gilkes ,  Sailesh Mansinh Merchant ,  Deepak A. Ramappa ,  Kurt George Steiner

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/538 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/528 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silane passivation process, carried out in-situ together with the formation of a subsequent dielectric film, converts the exposed Cu surfaces of a Cu interconnect structure, to copper silicide. The copper silicide suppresses Cu diffusion and electromigration and serves as a barrier material in regions where contact to further conductive material is made. An entire copper surface of a copper interconnect structure may be silicided or a local portion of the surface silicided after an opening is formed in an overlying dielectric to expose a portion of the copper surface.

摘要翻译： 与形成随后的电介质膜一起原位进行的硅烷钝化工艺将Cu互连结构的暴露的Cu表面转化为硅化铜。 铜硅化物抑制Cu扩散和电迁移，并在与其它导电材料接触的区域中用作阻挡材料。 铜互连结构的整个铜表面可以在覆盖电介质中形成开口以暴露铜表面的一部分之后被硅化或表面硅化的局部部分。

公开(公告)号：US08466039B2

公开(公告)日：2013-06-18

申请号：US13399637

申请日：2012-02-17

申请人： Deepak A. Ramappa ,  Julian G. Blake

发明人： Deepak A. Ramappa ,  Julian G. Blake

IPC分类号： H01L21/30

CPC分类号： H01L21/76254 ,  Y10S438/977

摘要： A method of cleaving a substrate is disclosed. A species, such as hydrogen or helium, is implanted into a substrate to form a layer of microbubbles. The substrate is then annealed a pressure greater than atmosphere. This annealing may be performed in the presence of the species that was implanted. This diffuses the species into the substrate. The substrate is then cleaved along the layer of microbubbles. Other steps to form an oxide layer or to bond to a handle also may be included.

摘要翻译： 公开了一种切割基板的方法。 将诸如氢或氦的物质植入衬底中以形成微泡层。 然后将衬底退火，压力大于大气压。 该退火可以在植入物种的存在下进行。 这将物种扩散到基质中。 然后沿着微泡层切割底物。 可以包括形成氧化物层或结合到手柄的其它步骤。

公开(公告)号：US20100279479A1

公开(公告)日：2010-11-04

申请号：US12434364

申请日：2009-05-01

申请人： Christopher R. Hatem ,  Helen L. Maynard ,  Deepak A. Ramappa

发明人： Christopher R. Hatem ,  Helen L. Maynard ,  Deepak A. Ramappa

IPC分类号： H01L21/30

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26593 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/7848

摘要： A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing one or more cold-carbon or molecular carbon ion implantation steps to implant carbon ions within the semiconductor structure to create strain layers on either side of a channel region. Raised source/drain regions are then formed above the strain layers, and subsequent ion implantation steps are used to dope the raised source/drain region. A millisecond anneal step activates the strain layers and the raised source/drain regions. The strain layers enhances carrier mobility within a channel region of the semiconductor structure, while the raised source/drain regions minimize reduction in strain in the strain layer caused by subsequent implantation of dopant ions in the raised source/drain regions.

摘要翻译： 公开了一种用于增强半导体结构的沟道区域中的拉伸应力的方法。 该方法包括执行一个或多个冷碳或分子碳离子注入步骤以在半导体结构内注入碳离子，以在沟道区的任一侧产生应变层。 然后在应变层上方形成升高的源极/漏极区域，并且随后的离子注入步骤用于掺杂升高的源极/漏极区域。 毫秒退火步骤激活应变层和升高的源极/漏极区域。 应变层增强了半导体结构的沟道区域内的载流子迁移率，而凸起的源极/漏极区域最小化了由于在升高的源极/漏极区域中随后注入掺杂剂离子引起的应变层中的应变减小。

公开(公告)号：US20100136781A1

公开(公告)日：2010-06-03

申请号：US12327336

申请日：2008-12-03

申请人： Makarand R. Kulkarni ,  Deepak A. Ramappa

发明人： Makarand R. Kulkarni ,  Deepak A. Ramappa

IPC分类号： H01L21/768 ,  G03F1/00

CPC分类号： H01L21/76807 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.

摘要翻译： 本发明的一个实施例涉及一种配置成利用单个光刻和蚀刻工艺形成金属化和通孔级的光刻掩模。 更具体地，包括掩模通孔形状和一个或多个金属线形状的光刻掩模被配置为产生晶片上金属线和通孔级。 掩模通孔形状对应于具有第一临界尺寸（CD）的经晶片上的光刻胶通孔开口。 一个或多个掩模线形状对应于分别具有第二CD的一个或多个晶片上的光致抗蚀剂丝线开口。 第一CD大于第二CD，从而为由光致抗蚀剂经由开口曝光的ILD提供比通过一个或多个光致抗蚀剂线开口暴露的ILD更大的垂直蚀刻速率。 CD中的这种差异导致在金属线水平面垂直延伸的通孔，从而与底层金属物理接触。