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公开(公告)号：US20170263561A1
公开(公告)日：2017-09-14
申请号：US15246481
申请日：2016-08-24
Applicant: Apple Inc.
Inventor： Anne M. Mason , Peter J. Johnston , Christine A. Laliberte , Dominic P. McCarthy , Shawn X. Arnold , Souvik Mukherjee
CPC classification number: H01L23/5386 , H01C7/00 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L24/17 , H01L25/18 , H01L2224/13147 , H01L2224/16227 , H01L2924/1434 , H01L2924/19043 , H05K1/113 , H05K1/167 , H05K1/181 , H05K3/3436 , H05K3/4076 , H05K2201/096 , H05K2201/10159 , H05K2201/10378 , H05K2201/10734 , Y02P70/613
Abstract: A routing apparatus includes a PCB having first and second arrays of contact pads, an interposer having third, fourth and fifth arrays of contact pads, the third and fourth arrays of contact pads being disposed on opposing surfaces of the interposer, the third array of contact pads being electrically connected to the first array of contact pads. First and second integrated circuits are respectively mounted on the second and fourth arrays of contact pads. The interposer includes a first group of conductive traces insulated from one another, a first array of conductive vias extending perpendicularly to the first group of conductive traces, the first array of conductive vias including through-vias connecting the third array of contact pads to corresponding contact pads in the fourth array of contact pads. The interposer further including isolation resistors embedded within the first array of conductive vias, each isolation resistor being configured to produce a copy of a signal flowing through the conductive via that is coupled to one end of the isolation resistor on the conductive trace that is coupled to an opposite end of the isolation resistor.
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Patent Agency Ranking
公开(公告)号：US09593991B2
公开(公告)日：2017-03-14
申请号：US14812958
申请日：2015-07-29
Applicant: Apple Inc.
Inventor： Anne M. Mason , Bryan McDonald , Shawn X. Arnold , Matthew Casebolt , Dennis R. Pyper
CPC classification number: G01L1/22 , G01L1/2262 , G01L1/2287 , G01L3/1457 , G01L5/0047 , G01M5/0033 , G01M5/0083
Abstract: A printed circuit board may have embedded strain gauges. A strain gauge may be formed from a metal trace on a polymer substrate. The metal trace may form a variable strain gauge resistor that is incorporated into a bridge circuit for a strain gauge. The printed circuit may have a rigid printed circuit layer with a recess that receives the polymer substrate. Metal pads on the polymer substrate may be coupled to respective ends of the variable strain gauge resistor. The rigid printed circuit substrate with the recess may be laminated between additional rigid printed circuit layers. Vias may be formed through the additional rigid printed circuit layers to contact the metal pads. Embedded strain gauges may be used in gathering strain data when strain is imparted to a printed circuit during use of the printed circuit in an electronic device or during testing.
Abstract translation: 印刷电路板可以具有嵌入式应变计。 应变计可由聚合物基底上的金属迹线形成。 金属痕迹可以形成可变应变计电阻器，其被并入用于应变仪的桥式电路中。 印刷电路可以具有刚性印刷电路层，其具有容纳聚合物基底的凹部。 聚合物基板上的金属焊盘可以连接到可变应变计电阻器的相应末端。 具有凹槽的刚性印刷电路基板可以层压在附加的刚性印刷电路层之间。 可以通过附加的刚性印刷电路层形成通孔以接触金属焊盘。 当在电子设备中使用印刷电路或在测试期间使用印刷电路时，嵌入式应变计可用于收集应变数据。
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公开(公告)号：US20220095455A1
公开(公告)日：2022-03-24
申请号：US17119126
申请日：2020-12-11
Applicant: Apple Inc.
Inventor： Anne M. Mason , Chad O. Simpson , William Hannon , Mark J. Beesley
Abstract: Structures that implement three-dimensional (3D) conductive material (e.g., copper) in printed circuit boards (PCBs) are disclosed. 3D (three-dimensional) conductive material may include trenches and/or buried vias that are filled with conductive material in the PCBs. Trenches may be formed in build-up layers of a PCB by overlapping multiple laser drilled vias. The trenches may be filled with conductive material using electroplating process(es). Buried vias may be formed through the core layers of the PCB by mechanical drilling. The buried via may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material. Various PCB structures are disclosed that implement combinations of these trenches and/or these buried vias filled with conductive material.
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公开(公告)号：US10420213B2
公开(公告)日：2019-09-17
申请号：US15696102
申请日：2017-09-05
Applicant: Apple Inc.
Inventor： Mark J. Beesley , Albert A. Onderick, II , Anne M. Mason , Craig A. Gammel , Shawn X. Arnold
Abstract: Printed circuit boards having an increased density of vertical interconnect paths, as well as methods for their manufacture. One example may provide a printed circuit board having an increased density of vertical interconnect paths by forming a plurality of segmented vias. The segmented vias may extend through interior layers of the printed circuit board. The segmented vias may be formed of portions of vias in the interior layers of the printed circuit board. An area between three or more segmented vias may be filled with resin or other material or materials.
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公开(公告)号：US09812401B2
公开(公告)日：2017-11-07
申请号：US15246481
申请日：2016-08-24
Applicant: Apple Inc.
Inventor： Anne M. Mason , Peter J. Johnston , Christine A. Laliberte , Dominic P. McCarthy , Shawn X. Arnold , Souvik Mukherjee
CPC classification number: H01L23/5386 , H01C7/00 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L24/17 , H01L25/18 , H01L2224/13147 , H01L2224/16227 , H01L2924/1434 , H01L2924/19043 , H05K1/113 , H05K1/167 , H05K1/181 , H05K3/3436 , H05K3/4076 , H05K2201/096 , H05K2201/10159 , H05K2201/10378 , H05K2201/10734 , Y02P70/613
Abstract: A routing apparatus includes a PCB having first and second arrays of contact pads, an interposer having third, fourth and fifth arrays of contact pads, the third and fourth arrays of contact pads being disposed on opposing surfaces of the interposer, the third array of contact pads being electrically connected to the first array of contact pads. First and second integrated circuits are respectively mounted on the second and fourth arrays of contact pads. The interposer includes a first group of conductive traces insulated from one another, a first array of conductive vias extending perpendicularly to the first group of conductive traces, the first array of conductive vias including through-vias connecting the third array of contact pads to corresponding contact pads in the fourth array of contact pads. The interposer further including isolation resistors embedded within the first array of conductive vias, each isolation resistor being configured to produce a copy of a signal flowing through the conductive via that is coupled to one end of the isolation resistor on the conductive trace that is coupled to an opposite end of the isolation resistor.
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公开(公告)号：US20170265304A1
公开(公告)日：2017-09-14
申请号：US15068474
申请日：2016-03-11
Applicant: Apple Inc.
Inventor： Anne M. Mason , Peter J. Johnston , Christine A. Laliberte , Dominic P. McCarthy , Shawn X. Arnold , Souvik Mukherjee
CPC classification number: H01L23/5386 , H01C7/00 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L24/17 , H01L25/18 , H01L2224/13147 , H01L2224/16227 , H01L2924/1434 , H01L2924/19043 , H05K1/113 , H05K1/167 , H05K1/181 , H05K3/3436 , H05K3/4076 , H05K2201/096 , H05K2201/10159 , H05K2201/10378 , H05K2201/10734 , Y02P70/613
Abstract: A circuit board includes conductive traces being sandwiched by an upper insulating layer and a lower insulating layer, a first array of conductive vias extending perpendicularly to the conductive traces, the vias in the first array of conductive vias being arranged such that any two adjacent vias in a row of vias extending along any given dimension in the first array of conductive vias are equally spaced from each other, and isolation resistors embedded within the first array of conductive vias such that each isolation resistor is disposed between at least two adjacent vias in the first array of conductive vias, each isolation resistor being disposed closer to the conductive via to which the isolation resistor is coupled than all other conductive vias surrounding the isolation resistor.
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