公开(公告)号：US11720360B2

公开(公告)日：2023-08-08

申请号：US17469504

申请日：2021-09-08

Applicant: Apple Inc.

Inventor： Jeff Gonion ,  John H. Kelm ,  James Vash ,  Pradeep Kanapathipillai ,  Mridul Agarwal ,  Gideon N. Levinsky ,  Richard F. Russo ,  Christopher M. Tsay

IPC: G06F9/30 ,  G06F12/02 ,  G06F12/0875 ,  G06F9/38

CPC classification number: G06F9/30087 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30101 ,  G06F9/3834 ,  G06F12/0238 ,  G06F12/0875

Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

公开(公告)号：US11550716B2

公开(公告)日：2023-01-10

申请号：US17648071

申请日：2022-01-14

Applicant: Apple Inc.

Inventor： Gaurav Garg ,  Sagi Lahav ,  Lital Levy-Rubin ,  Gerard Williams, III ,  Samer Nassar ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Jeff Gonion ,  James Vash

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/0891 ,  G06F9/46 ,  G06F13/16 ,  G06F12/0831

Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

公开(公告)号：US20240070090A1

公开(公告)日：2024-02-29

申请号：US18453108

申请日：2023-08-21

Applicant: Apple Inc.

Inventor： Jeff Gonion

IPC: G06F12/14

CPC classification number: G06F12/1408 ,  G06F12/1441

Abstract: In an embodiment, a system employs encryption on memory addresses generated by a source circuit that generates memory transactions (e.g., a processor such as a central processing unit (CPU), a graphics processing unit (GPU), various embedded processors or microcontrollers; or a peripheral device. The encrypted memory address corresponds to the row that is activated for the memory transaction, instead of the memory address generated by the source circuit.

公开(公告)号：US20230063676A1

公开(公告)日：2023-03-02

申请号：US17657524

申请日：2022-03-31

Applicant: Apple Inc.

Inventor： Sagi Lahav ,  Lital Levy - Rubin ,  Gaurav Garg ,  Gerard R. Williams, III ,  Samer Nassar ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Jeff Gonion

IPC: G06F9/46 ,  G06F9/32 ,  G06F9/50 ,  G06F9/30

Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a transaction pipeline and a pool of counters. The I/O agent circuit may initialize a first counter included in the pool of counters with an initial counter value. The I/O agent circuit may assign the first counter to a specific transaction type. The I/O agent circuit may increment the first counter as a part of allocating a transaction of a transaction type included in a set of transaction types different than the specific transaction type. Based on receiving a transaction request to process a first transaction of the specific transaction type, the I/O agent circuit may bind the first transaction to the first counter. The I/O agent circuit may issue the first transaction to the transaction pipeline based on a counter value stored by the first counter matching the initial counter value.

公开(公告)号：US20220318136A1

公开(公告)日：2022-10-06

申请号：US17648071

申请日：2022-01-14

Applicant: Apple Inc.

Inventor： Gaurav Garg ,  Sagi Lahav ,  Lital Levy - Rubin ,  Gerard Williams, III ,  Samer Nassar ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Jeff Gonion ,  James Vash

IPC: G06F12/06 ,  G06F12/0891 ,  G06F12/0831 ,  G06F13/16 ,  G06F9/46

Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

公开(公告)号：US20160148042A1

公开(公告)日：2016-05-26

申请号：US14980344

申请日：2015-12-28

Applicant: Apple Inc.

Inventor： Jeff Gonion ,  Duncan Robert Kerr

IPC: G06K9/00 ,  G06F3/0485 ,  G06F3/0482

Abstract: Systems and methods are provided for control of a personal computing device based on user face detection and recognition techniques.

Abstract translation: 系统和方法被提供用于基于用户面部检测和识别技术来控制个人计算设备。

公开(公告)号：US09223397B2

公开(公告)日：2015-12-29

申请号：US14090344

申请日：2013-11-26

Applicant: Apple Inc.

Inventor： Jeff Gonion ,  Duncan Robert Kerr

IPC: G06K9/00 ,  G06F3/00 ,  G06F1/32 ,  G06F21/32 ,  G06F21/62 ,  G06K9/62

CPC classification number: G06K9/00241 ,  G06F1/3231 ,  G06F3/005 ,  G06F3/0482 ,  G06F3/0485 ,  G06F21/32 ,  G06F21/629 ,  G06K9/00221 ,  G06K9/00288 ,  G06K9/6253 ,  Y02D10/173

Abstract: Systems and methods are provided for control of a personal computing device based on user face detection and recognition techniques.