公开(公告)号：US11430174B2

公开(公告)日：2022-08-30

申请号：US17150472

申请日：2021-01-15

Applicant: Apple Inc.

Inventor： Terence M. Potter ,  Richard W. Schreyer ,  James J. Ding ,  Alexander K. Kan ,  Michael Imbrogno

IPC: G06F12/00 ,  G06T15/00

Abstract: Techniques are disclosed relating to specifying memory consistency constraints. In some embodiments, an instruction may specify, for a memory operation, a type of memory consistency and a scope at which to enforce the type of consistency. For example, these fields may specify whether to sequence memory accesses relative to the operation at one or more of multiple different cache levels based on the type of memory consistency and the scope.

公开(公告)号：US20210134045A1

公开(公告)日：2021-05-06

申请号：US17150472

申请日：2021-01-15

Applicant: Apple Inc.

Inventor： Terence M. Potter ,  Richard W. Schreyer ,  James J. Ding ,  Alexander K. Kan ,  Michael Imbrogno

IPC: G06T15/00 ,  G06F12/00

Abstract: Techniques are disclosed relating to specifying memory consistency constraints. In some embodiments, an instruction may specify, for a memory operation, a type of memory consistency and a scope at which to enforce the type of consistency. For example, these fields may specify whether to sequence memory accesses relative to the operation at one or more of multiple different cache levels based on the type of memory consistency and the scope.

公开(公告)号：US20180182154A1

公开(公告)日：2018-06-28

申请号：US15388985

申请日：2016-12-22

Applicant: Apple Inc.

Inventor： Terence M. Potter ,  Richard W. Schreyer ,  James J. Ding ,  Alexander K. Kan ,  Michael Imbrogno

IPC: G06T15/00 ,  G06T15/80

CPC classification number: G06T15/005

Abstract: Techniques are disclosed relating to synchronizing access to pixel resources. Examples of pixel resources include color attachments, a stencil buffer, and a depth buffer. In some embodiments, hardware registers are used to track status of assigned pixel resources and pixel wait and pixel release instruction are used to synchronize access to the pixel resources. In some embodiments, other accesses to the pixel resources may occur out of program order. Relative to tracking and ordering pass groups, this weak ordering and explicit synchronization may improve performance and reduce power consumption. Disclosed techniques may also facilitate coordination between fragment rendering threads and auxiliary mid-render compute tasks.

公开(公告)号：US09952655B1

公开(公告)日：2018-04-24

申请号：US15177793

申请日：2016-06-09

Applicant: Apple Inc.

Inventor： Jason P. Jane ,  Richard W. Schreyer ,  Michael J. E. Swift ,  Gokhan Avkarogullari ,  Luc R. Semeria ,  Patrick Y. Law

IPC: G06F9/30 ,  G06T1/20 ,  G06F1/28 ,  G06F1/32 ,  G06F9/4401 ,  G06F9/44

CPC classification number: G06F1/3287 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3246 ,  G06F9/30145 ,  G06F9/442 ,  G06T1/20 ,  G06T2200/28

Abstract: In one embodiment, a system controls a duty cycle of a processor (e.g. a graphics processing unit (GPU)) to manage power. The GPU may include a snoop indicator that may control whether or not the GPU captures and/or responds to communications from another processor (e.g. a central processing unit (CPU) that executes a driver associate with the GPU). A snooze indicator may control whether or not the GPU is automatically repowered at the start of the next frame, or is repowered only if the communication indicating additional work has been received. In an embodiment, the GPU mode controls discussed above may permit the GPU firmware executed with the GPU itself to control duty cycle power down, independent of the driver executing on the CPU.

公开(公告)号：US10949944B2

公开(公告)日：2021-03-16

申请号：US16390577

申请日：2019-04-22

Applicant: Apple Inc.

Inventor： Richard W. Schreyer ,  Kenneth C. Dyke ,  Alexander K. Kan

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/54

Abstract: Systems, computer readable media, and methods for a unified programming interface and language are disclosed. In one embodiment, the unified programming interface and language assists program developers write multi-threaded programs that can perform both graphics and data-parallel compute processing on GPUs. The same GPU programming language model can be used to describe both graphics shaders and compute kernels, and the same data structures and resources may be used for both graphics and compute operations. Developers can use multithreading efficiently to create and submit command buffers in parallel.

公开(公告)号：US10930047B2

公开(公告)日：2021-02-23

申请号：US16707455

申请日：2019-12-09

Applicant: Apple Inc.

Inventor： Terence M. Potter ,  Richard W. Schreyer ,  James J. Ding ,  Alexander K. Kan ,  Michael Imbrogno

IPC: G06F12/00 ,  G06T15/00

Abstract: Techniques are disclosed relating to synchronizing access to pixel resources. Examples of pixel resources include color attachments, a stencil buffer, and a depth buffer. In some embodiments, hardware registers are used to track status of assigned pixel resources and pixel wait and pixel release instruction are used to synchronize access to the pixel resources. In some embodiments, other accesses to the pixel resources may occur out of program order. Relative to tracking and ordering pass groups, this weak ordering and explicit synchronization may improve performance and reduce power consumption. Disclosed techniques may also facilitate coordination between fragment rendering threads and auxiliary mid-render compute tasks.

公开(公告)号：US20200167986A1

公开(公告)日：2020-05-28

申请号：US16707455

申请日：2019-12-09

Applicant: Apple Inc.

Inventor： Terence M. Potter ,  Richard W. Schreyer ,  James J. Ding ,  Alexander K. Kan ,  Michael Imbrogno

IPC: G06T15/00 ,  G06F12/00

Abstract: Techniques are disclosed relating to synchronizing access to pixel resources. Examples of pixel resources include color attachments, a stencil buffer, and a depth buffer. In some embodiments, hardware registers are used to track status of assigned pixel resources and pixel wait and pixel release instruction are used to synchronize access to the pixel resources. In some embodiments, other accesses to the pixel resources may occur out of program order. Relative to tracking and ordering pass groups, this weak ordering and explicit synchronization may improve performance and reduce power consumption. Disclosed techniques may also facilitate coordination between fragment rendering threads and auxiliary mid-render compute tasks.

公开(公告)号：US20190361687A1

公开(公告)日：2019-11-28

申请号：US16532637

申请日：2019-08-06

Applicant: Apple Inc.

Inventor： Aaftab A. Munshi ,  Kenneth C. Dyke ,  Rahul U. Joshi ,  Richard W. Schreyer

IPC: G06F8/54 ,  G06F8/41

Abstract: A compiler and library provide the ability to compile a programming language according to a defined language model into a programming language independent, machine independent intermediate representation, for conversion into an executable on a target programmable device. The language model allows writing programs that perform data-parallel graphics and non-graphics tasks.

公开(公告)号：US20190251656A1

公开(公告)日：2019-08-15

申请号：US16390577

申请日：2019-04-22

Applicant: Apple Inc.

Inventor： Richard W. Schreyer ,  Kenneth C. Dyke ,  Alexander K. Kan

IPC: G06T1/20 ,  G06F9/54 ,  G06F9/30

CPC classification number: G06T1/20 ,  G06F9/30145 ,  G06F9/545 ,  G06T2200/28

Abstract: Systems, computer readable media, and methods for a unified programming interface and language are disclosed. In one embodiment, the unified programming interface and language assists program developers write multi-threaded programs that can perform both graphics and data-parallel compute processing on GPUs. The same GPU programming language model can be used to describe both graphics shaders and compute kernels, and the same data structures and resources may be used for both graphics and compute operations. Developers can use multithreading efficiently to create and submit command buffers in parallel.

公开(公告)号：US10223822B2

公开(公告)日：2019-03-05

申请号：US15388915

申请日：2016-12-22

Applicant: Apple Inc.

Inventor： Terence M. Potter ,  Ralph C. Taylor ,  Richard W. Schreyer ,  Aaftab A. Munshi ,  Justin A. Hensley

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/80 ,  G06T15/00 ,  G06F9/50 ,  G06F9/54

Abstract: Techniques are disclosed relating to performing mid-render auxiliary compute tasks for graphics processing. In some embodiments, auxiliary compute tasks are performed during a render pass, using at least a portion of a memory context of the render pass, without accessing a shared memory during the render pass. Relative to flushing render data to shared memory to perform compute tasks, this may reduce memory accesses and/or cache thrashing, which may in turn increase performance and/or reduce power consumption.