公开(公告)号：US20230064183A1

公开(公告)日：2023-03-02

申请号：US17897375

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Ashish Pal ,  El Mehdi Bazizi ,  Andrew Yeoh ,  Nitin K. Ingle ,  Arvind Sundarrajan ,  Guan Huei See ,  Martinus Maria Berkens ,  Sameer A. Deshpande ,  Balasubramanian Pranatharthiharan ,  Yen-Chu Yang

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.

公开(公告)号：US20230040606A1

公开(公告)日：2023-02-09

申请号：US17879088

申请日：2022-08-02

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Saurabh Chopra ,  Myungsun Kim ,  Balasubramanian Pranatharthiharan

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is crystallized. Epitaxially growth of the source and drain regions then proceeds, which growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

公开(公告)号：US20250117754A1

公开(公告)日：2025-04-10

申请号：US18903907

申请日：2024-10-01

Applicant: Applied Materials, Inc.

Inventor： Ruiying Hao ,  Winston Chen ,  Jenn-Yue Wang ,  Cathy Cai ,  Weizong Xu ,  Lifan Chen ,  Balasubramanian Pranatharthiharan

IPC: G06Q10/20 ,  G06T7/00 ,  G06V10/48 ,  G06V10/88

Abstract: A method includes obtaining, by a processing device, first image data of a substrate including an epitaxial film. The method further includes applying a frequency domain filter to the first image data to obtain filtered image data. The method further includes determining a number of epitaxial defects represented in the first image data by performing feature detection on the filtered image data. The method further includes performing a corrective action in view of the number of epitaxial defects.

公开(公告)号：US20250022935A1

公开(公告)日：2025-01-16

申请号：US18761490

申请日：2024-07-02

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Raghuveer Satya Makala ,  Naomi Yoshida ,  Hsueh Chung Chen ,  Balasubramanian Pranatharthiharan

IPC: H01L29/49 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Methods of manufacturing memory devices are provided. The method comprises forming a first epitaxial layer on a substrate; and forming a memory array on the first epitaxial layer, the memory array comprising a memory stack of alternating layers of an oxide material and a metal material on the first epitaxial layer, at least one memory cell extending from the first epitaxial layer through the memory stack, and a slit filled with a fill material adjacent to the at least one memory cell.

公开(公告)号：US20240290885A1

公开(公告)日：2024-08-29

申请号：US18441886

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi ,  Hui Zhao ,  Ashish Pal

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L21/76831 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain. Devices include a first gate region having a first self-aligned single diffusion break in a n-MOS region, and a second gate region includes having a self-aligned single diffusion break in a p-MOS region. The second self-aligned single diffusion break also contains a liner and a compressive stressed material, where the stressed metal fill exhibits a compressive stress of about 350 MPa or greater.

公开(公告)号：US20240038553A1

公开(公告)日：2024-02-01

申请号：US18225799

申请日：2023-07-25

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  Lequn Liu ,  Brian K. Kirkpatrick

IPC: H01L21/67 ,  H01L29/66

CPC classification number: H01L21/67069 ,  H01L29/66545 ,  H01L21/67075 ,  H01L21/67167 ,  H01L21/67207 ,  H01L29/66439 ,  H01L29/0673

Abstract: Semiconductor devices (e.g., GAA device structures) and processing methods and cluster tools for forming GAA device structures are described. The cluster tools for forming GAA device structures comprise a first etch chamber, a second etch chamber, and a third etch chamber. Each of the first etch chamber and the second etch chamber independently comprises a single-wafer chamber or an immersion chamber. One or more of the first etch chamber or the second etch chamber may be a wet etch chamber. In some embodiments, at least one of the first etch chamber, the second etch chamber, and the third etch chamber is a dry etch chamber. The cluster tool described herein advantageously reduces the number of cleaning processes, the total time between cleaning and processing operations, variations in time between processing and variation in sidewall loss compared to conventional cluster tools.

公开(公告)号：US20240014214A1

公开(公告)日：2024-01-11

申请号：US18219993

申请日：2023-07-10

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Jody A. Fronheiser ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi ,  Ashish Pal

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/15 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L29/66545 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/15 ,  H01L29/66439 ,  H01L21/823807 ,  H01L29/0673

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding material on a first material followed by a dry oxidation process resulting rearrangement of the cladding material and first material.

公开(公告)号：US20230170400A1

公开(公告)日：2023-06-01

申请号：US17994520

申请日：2022-11-28

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Benjamin Colombeau ,  El Mehdi Bazizi ,  Balasubramanian Pranatharthiharan

IPC: H01L29/66 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L29/66439 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/02532 ,  H01L29/401 ,  H01L29/66545

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a source/drain cavity and filling the cavity with a sacrificial layer. The sacrificial layer is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.

公开(公告)号：US20230068312A1

公开(公告)日：2023-03-02

申请号：US17897378

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Ashish Pal ,  El Mehdi Bazizi ,  Andrew Yeoh ,  Nitin K. Ingle ,  Arvind Sundarrajan ,  Guan Huei See ,  Martinus Maria Berkens ,  Sameer A. Deshpande ,  Balasubramanian Pranatharthiharan ,  Yen-Chu Yang

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/48

Abstract: Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.

公开(公告)号：US20250142957A1

公开(公告)日：2025-05-01

申请号：US18911689

申请日：2024-10-10

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Steven C.H. Hung ,  Veeraraghavan S. Basker ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan

IPC: H01L27/118

Abstract: Logic devices and methods of manufacturing logic devices are provided. The semiconductor logic device includes an n-channel gate-all-around (n-GAA) field-effect transistor on a substrate integrated with a p-channel gate-all-around (p-GAA) field-effect transistor on the substrate adjacent to the n-channel gate-all-around (p-GAA) field-effect transistor. The n-channel gate-all-around (n-GAA) field effect-transistor has a structure including a plurality of layers comprising silicon and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs extending between a source region and a drain region, and the p-channel gate-all-around (p-GAA) field-effect transistor has a plurality of layers comprising in a range of from 5% to 15% germanium and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs.