公开(公告)号：US20230064183A1

公开(公告)日：2023-03-02

申请号：US17897375

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Ashish Pal ,  El Mehdi Bazizi ,  Andrew Yeoh ,  Nitin K. Ingle ,  Arvind Sundarrajan ,  Guan Huei See ,  Martinus Maria Berkens ,  Sameer A. Deshpande ,  Balasubramanian Pranatharthiharan ,  Yen-Chu Yang

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.

公开(公告)号：US11421316B2

公开(公告)日：2022-08-23

申请号：US16584695

申请日：2019-09-26

Applicant: APPLIED MATERIALS, INC.

Inventor： Prayudi Lianto ,  Mohamed Rafi ,  Muhammad Azim Bin Syed Sulaiman ,  Guan Huei See ,  Ang Yu Xin Kristy ,  Karthik Elumalai ,  Sriskantharajah Thirunavukarasu ,  Arvind Sundarrajan

IPC: H01L23/48 ,  H01L23/52 ,  C23C14/54 ,  H01L21/67 ,  H01L23/00

Abstract: Methods and apparatus for producing fine pitch patterning on a substrate. Warpage correction of the substrate is accomplished on a carrier or carrier-less substrate. A first warpage correction process is performed on the substrate by raising and holding a temperature of the substrate to a first temperature and cooling the carrier-less substrate to a second temperature. Further wafer level packaging processing is then performed such as forming vias in a polymer layer on the substrate. A second warpage correction process is then performed on the substrate by raising and holding a temperature of the substrate to a third temperature and cooling the substrate to a fourth temperature. With the warpage of the substrate reduced, a redistribution layer may be formed on the substrate with a 2/2 μm l/s fine pitch patterning.

公开(公告)号：US11309278B2

公开(公告)日：2022-04-19

申请号：US16520680

申请日：2019-07-24

Applicant: APPLIED MATERIALS, INC.

Inventor： Prayudi Lianto ,  Guan Huei See ,  Sriskantharajah Thirunavukarasu ,  Arvind Sundarrajan ,  Xundong Dai ,  Peter Khai Mum Fung

IPC: G11C16/04 ,  H01L23/00 ,  B23K101/40 ,  B23K20/02

Abstract: Methods for bonding substrates used, for example, in substrate-level packaging, are provided herein. In some embodiments, a method for bonding substrates includes: performing electrochemical deposition (ECD) to deposit at least one material on each of a first substrate and a second substrate, performing chemical mechanical polishing (CMP) on the first substrate and the second substrate to form a bonding interface on each of the first substrate and the second substrate, positioning the first substrate on the second substrate so that the bonding interface on the first substrate aligns with the bonding interface on the second substrate, and bonding the first substrate to the second substrate using the bonding interface on the first substrate and the bonding interface on the second substrate.

公开(公告)号：US10319601B2

公开(公告)日：2019-06-11

申请号：US15467866

申请日：2017-03-23

Applicant: Applied Materials, Inc.

Inventor： Ranga Rao Arnepalli ,  Prerna Goradia ,  Prayudi Lianto ,  Jie Zeng ,  Arvind Sundarrajan ,  Robert Jan Visser ,  Guan Huei See

IPC: H01L21/3105 ,  H01L21/3205 ,  C09G1/02 ,  C09K3/14 ,  C09G1/00 ,  C09G1/04 ,  C09G1/06 ,  C09K13/06 ,  B24B1/00 ,  B24B37/04 ,  H01L21/306

Abstract: A slurry for chemical mechanical planarization includes water, 1-3 wt. % of abrasive particles having an average diameter of at least 10 nm and less than 100 nm and an outer surface of ceria, and ½-3 wt. % of at least one amine.

公开(公告)号：US10276424B2

公开(公告)日：2019-04-30

申请号：US15638798

申请日：2017-06-30

Applicant: APPLIED MATERIALS, INC.

Inventor： Guan Huei See ,  Yu Gu ,  Arvind Sundarrajan

IPC: H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

Abstract: Methods and apparatus for wafer level packaging are described herein. According to one embodiment, a method comprises depositing an adhesive layer atop a carrier, placing at least a portion of a substrate pre-fabricated with a plurality of die cavities and a plurality of through vias atop the laminate, inserting a die into each of the die cavities, encapsulating the die and the substrate and debonding and removing the laminate and the carrier from the encapsulated die and substrate. Another embodiment provides an apparatus comprising a substrate, a plurality of die cavities formed through the substrate and a plurality of conductive through vias disposed through the substrate and arranged about the perimeter of each die cavity, wherein a top surface of the substrate is exposed for application of an encapsulating layer and a bottom surface of the substrate is exposed for placement on an adhesive layer.

公开(公告)号：US09993853B2

公开(公告)日：2018-06-12

申请号：US14556085

申请日：2014-11-28

Applicant: APPLIED MATERIALS, INC.

Inventor： Sriskantharajah Thirunavukarasu ,  Jen Sern Lew ,  Arvind Sundarrajan ,  Srinivas D. Nemani

IPC: B08B3/04 ,  B08B5/02 ,  B08B6/00 ,  H01L21/67 ,  H01L21/683

CPC classification number: B08B5/02 ,  B08B6/00 ,  H01L21/67028 ,  H01L21/6831 ,  H01L21/6838

Abstract: Embodiments of methods and apparatus for removing particles from a surface of a substrate, such as from the backside of the substrate, are provided herein. In some embodiments, an apparatus for removing particles from a surface of a substrate includes: a substrate handler to expose the surface of the substrate; a particle separator to separate particles from the exposed surface of the substrate; a particle transporter to transport the separated particles; and a particle collector to collect the transported particles.

公开(公告)号：US09472392B2

公开(公告)日：2016-10-18

申请号：US14610863

申请日：2015-01-30

Applicant: Applied Materials, Inc.

Inventor： Zongbin Wang ,  Shalina Sudheeran ,  Loke Yuen Wong ,  Arvind Sundarrajan

IPC: H01L21/31 ,  H01L21/02

CPC classification number: H01L21/02164 ,  C23C16/045 ,  C23C16/401 ,  C23C16/45536 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0228

Abstract: Silicon oxide is deposited with improved step coverage by first exposing a patterned substrate to a silicon-containing precursor and then to an oxygen-containing precursor or vice versa. Plasma excitation is used for both precursors. Exposing the precursors one-at-a-time avoids disproportionate deposition of silicon oxide near the opening of a high aspect ratio gap on a patterned substrate. The plasma-excited precursors exhibit a lower sticking coefficient and/or higher surface diffusion rate in regions already adsorbed and therefore end up depositing silicon oxide deep within the high aspect ratio gap to achieve the improvement in step coverage.

Abstract translation: 通过首先将图案化的衬底暴露于含硅前体，然后再暴露于含氧前体，反之亦然，沉积氧化硅。 等离子体激发用于两种前体。 一次性暴露前体避免了在图案化基底上的高纵横比间隙的开口附近氧化硅不成比例的沉积。 等离子体激发的前体在已经吸附的区域中表现出较低的粘附系数和/或较高的表面扩散速率，因此最终在高纵横比间隙内沉积氧化硅以达到步骤覆盖的改善。

公开(公告)号：US20160225614A1

公开(公告)日：2016-08-04

申请号：US14610863

申请日：2015-01-30

Applicant: APPLIED MATERIALS, INC.

Inventor： Zongbin Wang ,  Shalina Sudheeran ,  Loke Yuen Wong ,  Arvind Sundarrajan

IPC: H01L21/02

CPC classification number: H01L21/02164 ,  C23C16/045 ,  C23C16/401 ,  C23C16/45536 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0228

Abstract: Silicon oxide is deposited with improved step coverage by first exposing a patterned substrate to a silicon-containing precursor and then to an oxygen-containing precursor or vice versa. Plasma excitation is used for both precursors. Exposing the precursors one-at-a-time avoids disproportionate deposition of silicon oxide near the opening of a high aspect ratio gap on a patterned substrate. The plasma-excited precursors exhibit a lower sticking coefficient and/or higher surface diffusion rate in regions already adsorbed and therefore end up depositing silicon oxide deep within the high aspect ratio gap to achieve the improvement in step coverage.

Abstract translation: 通过首先将图案化的衬底暴露于含硅前体，然后再暴露于含氧前体，反之亦然，沉积氧化硅。 等离子体激发用于两种前体。 一次性暴露前体避免了在图案化基底上的高纵横比间隙的开口附近氧化硅不成比例的沉积。 等离子体激发的前体在已经吸附的区域中表现出较低的粘附系数和/或较高的表面扩散速率，因此最终在高纵横比间隙内沉积氧化硅以达到步骤覆盖的改善。

公开(公告)号：US10651126B2

公开(公告)日：2020-05-12

申请号：US15835909

申请日：2017-12-08

Applicant: APPLIED MATERIALS, INC.

Inventor： Chien-Kang Hsiung ,  Arvind Sundarrajan

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/538 ,  H01L21/66 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: A wafer-level bridge die is affixed with an adhesive layer to a redistribution layer (RDL) that has been temporarily bonded to a carrier. Electrical interconnects are formed on the RDL and on the bridge die and encapsulated in a first mold layer. A plurality of dies are coupled to the RDL and the bridge die such that a die is electrically connected to at least one electrical interconnect of the RDL and to at least one electrical interconnect of the bridge die. A second mold layer is formed on the first mold layer to encapsulate the plurality of dies. The temporary bond is then broken and the carrier is removed, exposing the RDL connections.

公开(公告)号：US10475735B2

公开(公告)日：2019-11-12

申请号：US15623704

申请日：2017-06-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Peng Suo ,  Guan Huei See ,  Arvind Sundarrajan

IPC: H01L23/498 ,  H01L21/8234 ,  H01L49/02 ,  H01L27/02 ,  H01L23/522 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: Methods of processing a substrate include: providing a substrate with a first polymer dielectric layer; forming a first RDL on the first polymer dielectric layer; constructing a 3D MIM capacitive stack on the first RDL in at least one opening in a top surface of a second polymer dielectric layer, the 3D MIM capacitive stack having a top electrode, a bottom electrode, and a capacitive dielectric layer interposed between the top electrode and the bottom electrode; depositing a dielectric layer on the 3D MIM capacitive stack and on the second polymer dielectric layer; and removing a portion of the dielectric layer to expose at least a portion of the top electrode at a bottom of at least one opening of the 3D MIM capacitive stack and to expose at least a portion of the metal layer at a bottom of at least one opening of the second polymer dielectric layer.