公开(公告)号：US20150255507A1

公开(公告)日：2015-09-10

申请号：US14201439

申请日：2014-03-07

Applicant: Applied Materials, Inc.

Inventor： Mahendra PAKALA ,  Mihaela BALSEANU ,  Jonathan GERMAIN ,  Jaesoo AHN ,  Lin XUE

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: A method for fabricating an MRAM bit that includes depositing a spacer layer that protects the tunneling barrier layer during processing is disclosed. The deposited spacer layer prevents byproducts formed in later processing from redepositing on the tunneling barrier layer. Such redeposition may lead to product failure and decreased manufacturing yield. The method further includes non-corrosive processing conditions that prevent damage to the layers of MRAM bits. The non-corrosive processing conditions may include etching without using a halogen-based plasma. Embodiments disclosed herein use an etch-deposition-etch sequence that simplifies processing.

Abstract translation: 公开了一种用于制造MRAM位的方法，其包括在处理期间沉积保护隧道势垒层的间隔层。 沉积的间隔层防止在后续处理中形成的副产物再沉积在隧道势垒层上。 这种再沉积可能导致产品失效并降低了制造成品率。 该方法还包括防腐损坏处理条件，以防损坏MRAM位的层。 非腐蚀性处理条件可以包括不使用卤素等离子体的蚀刻。 本文公开的实施例使用简化处理的蚀刻 - 沉积蚀刻序列。

公开(公告)号：US20220115439A1

公开(公告)日：2022-04-14

申请号：US17423435

申请日：2020-01-16

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chando PARK ,  Jaesoo AHN ,  Hsin-wei TSENG ,  Mahendra PAKALA

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Implementations of the present disclosure generally relate to a memory device. More specifically, implementations described herein generally relate to a SOT-MRAM. The SOT-MRAM includes a memory cell having a magnetic storage layer disposed side by side and in contact with a SOT layer. The side by side magnetic storage layer and the SOT layer can achieve the switching of the magnetic storage layer by reversing the direction of the electrical current flowing through the SOT layer without any additional conditions.

公开(公告)号：US20210351342A1

公开(公告)日：2021-11-11

申请号：US16871779

申请日：2020-05-11

Applicant: Applied Materials, Inc.

Inventor： Minrui YUI ,  Wenhui WANG ,  Jaesoo AHN ,  Jong Mun KIM ,  Sahil PATEL ,  Lin XUE ,  Chando PARK ,  Mahendra PAKALA ,  Chentsau Chris YING ,  Huixiong DAI ,  Christopher S. Ngai

IPC: H01L43/08 ,  H01L43/04 ,  H01L43/14 ,  H01L43/10 ,  G11C11/16 ,  H01L27/22 ,  G01R33/09

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

公开(公告)号：US20200098981A1

公开(公告)日：2020-03-26

申请号：US16141470

申请日：2018-09-25

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Jaesoo AHN ,  Hsin-wei TSENG ,  Mahendra PAKALA

IPC: H01L43/12 ,  H01L43/10

Abstract: Embodiments of the disclosure relate to methods for fabricating structures used in memory devices. More specifically, embodiments of the disclosure relate to methods for fabricating MTJ structures in memory devices. In one embodiment, the method includes forming a MTJ structure, depositing a encapsulating layer on a top and sides of the MTJ structure, depositing a dielectric material on the encapsulating layer, removing the dielectric material and the encapsulating layer disposed on the top of the MTJ structure by a chemical mechanical planarization (CMP) process to expose the top of the MTJ structure, and depositing a contact layer on the MTJ structure. The method utilizes a CMP process to expose the top of the MTJ structure instead of an etching process, which avoids damaging the MTJ structure and leads to improved electrical contact between the MTJ structure and the contact layer.

公开(公告)号：US20190027169A1

公开(公告)日：2019-01-24

申请号：US15862301

申请日：2018-01-04

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chi Hong CHING ,  Jaesoo AHN ,  Mahendra PAKALA ,  Rongjun WANG

IPC: G11B5/39 ,  G11C11/15 ,  G11B5/31

Abstract: Embodiments herein provide film stacks utilized to form a magnetic tunnel junction (MTJ) structure on a substrate, comprising: a buffer layer; a seed layer disposed over the buffer layer; a first pinning layer disposed over the seed layer; a synthetic ferrimagnet (SyF) coupling layer disposed over the first pinning layer; a second pinning layer disposed over the SyF coupling layer; a structure blocking layer disposed over the second pinning layer; a magnetic reference layer disposed over the structure blocking layer; a tunnel barrier layer disposed over the magnetic reference layer; a magnetic storage layer disposed over the tunnel barrier layer; a capping layer disposed over the magnetic storage layer, wherein the capping layer comprises one or more layers; and a hard mask disposed over the capping layer, wherein at least one of the capping layer, the buffer layer, and the SyF coupling layer is not fabricated from Ru.

公开(公告)号：US20170170393A1

公开(公告)日：2017-06-15

申请号：US15438420

申请日：2017-02-21

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Jaesoo AHN ,  Mahendra PAKALA ,  Chi Hong CHING ,  Rongjun WANG

IPC: H01L43/12 ,  H01F10/32 ,  H01F10/14 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/12 ,  H01F10/14 ,  H01F10/3222 ,  H01L43/08 ,  H01L43/10

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one example, a film stack utilized to form a magnetic tunnel junction structure on a substrate includes a pinned layer disposed on a substrate, wherein the pinned layer comprises multiple layers including at least one or more of a Co containing layer, Pt containing layer, Ta containing layer, an Ru containing layer, an optional structure decoupling layer disposed on the pinned magnetic layer, a magnetic reference layer disposed on the optional structure decoupling layer, a tunneling barrier layer disposed on the magnetic reference layer, a magnetic storage layer disposed on the tunneling barrier layer, and a capping layer disposed on the magnetic storage layer.

公开(公告)号：US20220005831A1

公开(公告)日：2022-01-06

申请号：US17479789

申请日：2021-09-20

Applicant: Applied Materials, Inc.

Inventor： Jaesoo AHN ,  Thomas KWON ,  Mahendra PAKALA

IPC: H01L27/11597 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.

公开(公告)号：US20210119119A1

公开(公告)日：2021-04-22

申请号：US17112484

申请日：2020-12-04

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chando PARK ,  Chi Hong CHING ,  Jaesoo AHN ,  Mahendra PAKALA

IPC: H01L43/12 ,  H01F10/32 ,  H01L43/02 ,  G11C11/16 ,  H01L43/10 ,  H01F41/32 ,  C23C14/06 ,  C23C14/54

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a magnetic tunnel junction (MTJ) device structure includes a junction structure disposed on a substrate, the junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a dielectric capping layer disposed on the junction structure, a metal capping layer disposed on the junction structure, and a top buffer layer disposed on the metal capping layer.

公开(公告)号：US20200160884A1

公开(公告)日：2020-05-21

申请号：US16773232

申请日：2020-01-27

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chi Hong CHING ,  Jaesoo AHN ,  Mahendra PAKALA ,  Rongjun WANG

IPC: G11B5/39 ,  H01L21/768 ,  G11C11/15 ,  G11B5/31 ,  G11C11/16

Abstract: Embodiments herein provide film stacks that include a buffer layer; a synthetic ferrimagnet (SyF) coupling layer; and a capping layer, wherein the capping layer comprises one or more layers, and wherein the capping layer, the buffer layer, the SyF coupling layer, or a combination thereof, is not fabricated from Ru.

公开(公告)号：US20180108831A1

公开(公告)日：2018-04-19

申请号：US15712185

申请日：2017-09-22

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Sajjad Amin HASSAN ,  Mahendra PAKALA ,  Jaesoo AHN

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A process sequence is provided to provide an ultra-smooth (0.2 nm or less) bottom electrode surface for depositing magnetic tunnel junctions thereon. In one embodiment, the sequence includes forming a bottom electrode pad through bulk layer deposition followed by patterning and etching. Oxide is then deposited over the formed bottom electrode pads and polished back to expose the bottom electrode pads. A bottom electrode buff layer is then deposited thereover following a pre-clean operation. The bottom electrode buff layer is then exposed to a CMP process to improve surface roughness. An MTJ deposition is then performed over the bottom electrode buff layer.