公开(公告)号：US20190303523A1

公开(公告)日：2019-10-03

申请号：US15939047

申请日：2018-03-28

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Stephen Lewis Moore ,  Saurabh Pijuskumar Sinha

IPC: G06F17/50 ,  H01L27/02 ,  H01L23/522

Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized or legal locations.

公开(公告)号：US20190163860A1

公开(公告)日：2019-05-30

申请号：US15826649

申请日：2017-11-29

Applicant: Arm Limited

Inventor： Divya Madapusi Srinivas Prasad ,  Saurabh Pijuskumar Sinha ,  Brian Tracy Cline ,  Stephen Lewis Moore

IPC: G06F17/50

Abstract: Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.

公开(公告)号：US10002222B2

公开(公告)日：2018-06-19

申请号：US15210109

申请日：2016-07-14

Applicant: ARM Limited

Inventor： Brian Tracy Cline ,  Gregory Munson Yeric

IPC: G06F17/50 ,  G06F19/00 ,  G21K5/00 ,  G03F1/00 ,  H01L23/528 ,  H01L21/768

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G03F7/2022 ,  G06F17/5045 ,  G06F17/5077 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00 ,  H01L21/76892 ,  H01L23/522 ,  H01L23/528

Abstract: A method for modifying metal portions of a layout data file associated with a self-aligned multiple patterning (SAMP) process. The method comprises receiving the layout data file that includes one or more active metal portions and layout information associated with an integrated circuit. The method also comprises converting the layout data file to further include mask information having at least a first set of trim features associated with one or more redundant metal portions and one or more active metal portions of the layout data file. The method also comprises determining the one or more redundant metal portions to be perforated. The method further comprises modifying the mask information to further include a second set of trim features for perforating the one or more redundant metal portions. The first set of trim features and the second set of trim features are associated with a trim mask of the SAMP process.

公开(公告)号：US20230062482A1

公开(公告)日：2023-03-02

申请号：US17798518

申请日：2021-02-08

Applicant: Arm Limited

Inventor： Divya Madapusi Srinivas Prasad ,  David Victor Pietromonaco ,  Brian Tracy Cline

IPC: G06F30/367

Abstract: According to one implementation of the present disclosure, a method includes providing one or more tuning parameters of a transistor device at a first temperature of a range of temperatures below a temperature threshold; and adjusting the one or more tuning parameters until one or more second parameters of the transistor device corresponds to substantially the same value at the first temperature as a second temperature above the temperature threshold.

公开(公告)号：US20210389520A1

公开(公告)日：2021-12-16

申请号：US17288498

申请日：2019-10-23

Applicant: Arm Limited

Inventor： Vinay Vashishtha ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha ,  Gregory Munson Yeric

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/42

Abstract: Disclosed are devices and techniques for facilitating transmission of light signals between optical waveguides formed on integrated circuit (IC) devices. In an implementation, one or more first waveguides may be formed in a structure such that at least a portion of the one or more first waveguides are exposed for optical connectivity. The structure may comprise first features to enable the structure to be interlocked with an IC device comprising second features complementary with the first features, so as to align at least a portion of the one or more first waveguides exposed to optically couple with one or more second waveguides formed in the first integrated circuit device.

公开(公告)号：US11120191B2

公开(公告)日：2021-09-14

申请号：US16820471

申请日：2020-03-16

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Stephen Lewis Moore ,  Saurabh Pijuskumar Sinha

IPC: G06F30/392 ,  H01L27/02 ,  H01L23/522 ,  G06F111/04 ,  G06F111/20

Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized locations or legal locations.

公开(公告)号：US10796053B2

公开(公告)日：2020-10-06

申请号：US16140461

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Paul de Dood ,  Marlin Wayne Frederick, Jr. ,  Jerry Chaoyuan Wang ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50 ,  G06F30/39 ,  G06F30/30 ,  G06F30/398 ,  G06F30/392 ,  G06F30/394

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US10657218B2

公开(公告)日：2020-05-19

申请号：US15826649

申请日：2017-11-29

Applicant: Arm Limited

Inventor： Divya Madapusi Srinivas Prasad ,  Saurabh Pijuskumar Sinha ,  Brian Tracy Cline ,  Stephen Lewis Moore

IPC: G06F17/50

Abstract: Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.

公开(公告)号：US20190325959A1

公开(公告)日：2019-10-24

申请号：US15960365

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Brian Tracy Cline ,  George McNeil Lattimore ,  Bal S. Sandhu

IPC: G11C14/00 ,  G11C13/00 ,  G11C7/06

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.

公开(公告)号：US20190325919A1

公开(公告)日：2019-10-24

申请号：US15960405

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Shidhartha Das ,  George McNeil Lattimore ,  Brian Tracy Cline

IPC: G11C5/06 ,  G11C14/00 ,  G11C8/10

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.